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Merge pull request #372 from serveln/vhdl_mode
Vhdl mode
2 parents d9a9ec2 + fb56cb4 commit d39c424

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17 files changed

+111
-0
lines changed

17 files changed

+111
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lines changed

snippets/vhdl-mode/architecture

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# -*- mode: snippet -*-
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# name: architecture
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# key: arch
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# --
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architecture ${1:Type} of ${2:Name} is
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begin
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$0
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end $1;

snippets/vhdl-mode/assignation

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# -*- mode: snippet -*-
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# name: assignation
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# key: asg
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# --
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${1:variable} <= ${2:value};

snippets/vhdl-mode/case

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# -*- mode: snippet -*-
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# name: case
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# key: case
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# --
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case ${1:cond} is
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when ${2:Value} =>
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$0
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end case;

snippets/vhdl-mode/component

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# -*- mode: snippet -*-
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# name: component
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# key: comp
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# --
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component ${1:Name}
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$0
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end component;

snippets/vhdl-mode/constant

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# -*- mode: snippet -*-
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# name: constant
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# key: const
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# --
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constant ${1:Name}: ${2:Type} := ${3:Value};

snippets/vhdl-mode/downto

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# -*- mode: snippet -*-
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# name: downto
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# key: dto
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# --
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${1:name}(${2:start} downto ${3:end})$0

snippets/vhdl-mode/entity

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# -*- mode: snippet -*-
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# name: entity
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# key: ent
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# --
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entity ${1:Name} is
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$0
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end $1;

snippets/vhdl-mode/if

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# -*- mode: snippet -*-
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# name: if
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# key: if
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# --
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if ${1:cond} then
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$0
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end if;

snippets/vhdl-mode/ifelif

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# -*- mode: snippet -*-
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# name: ifelif
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# key: ifelif
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# --
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if ${1:cond1} then
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$0
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elsif ${2:cond2} then
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end if;

snippets/vhdl-mode/ifelse

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# -*- mode: snippet -*-
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# name: ifelse
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# key: ifel
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# --
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if ${1:cond1} then
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$0
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else
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end if;

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