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Small fixes in timing output. (#43)
On Sail, use minstret instead of mcycle, since it gives a useful number and mcycle does not.
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3 files changed

+11
-13
lines changed

3 files changed

+11
-13
lines changed

benchmarks/allocation/alloc.cc

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,12 @@ using Debug = ConditionalDebug<DEBUG_ALLOCBENCH, "Allocator benchmark">;
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*/
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void __cheri_compartment("allocbench") run()
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{
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// Make sure sail doesn't print annoying log messages in the middle of the
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// output the first time that allocation happens.
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free(malloc(16));
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heap_quarantine_empty();
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MessageBuilder<ImplicitUARTOutput> out;
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out.format("#board\tsize\ttime");
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out.format("#board\tsize\ttime\n");
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const size_t MinimumSize = 32;
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const size_t MaximumSize = 131072;
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const size_t TotalSize = 1024 * 1024;

benchmarks/timing.h

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,12 +8,9 @@ namespace
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{
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int cycles;
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#ifdef SAIL
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// The Sail model doesn't implement the unprivileged cycle CSR in
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// M-mode only configurations, so we use mcycle instead. This requires
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// that mcycle is accessible read-only without the ASR permission.
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// Probably Sail should have the cycle CSR even without U-mode but need
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// clarification on spec.
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__asm__ volatile("csrr %0, mcycle" : "=r"(cycles));
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// On Sail, report the number of instructions, the cycle count is
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// meaningless.
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__asm__ volatile("csrr %0, minstret" : "=r"(cycles));
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#else
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__asm__ volatile("rdcycle %0" : "=r"(cycles));
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#endif

tests/test-runner.cc

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -16,12 +16,9 @@ namespace
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{
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int cycles;
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#ifdef SAIL
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// The Sail model doesn't implement the unprivileged cycle CSR in
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// M-mode only configurations, so we use mcycle instead. This requires
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// that mcycle is accessible read-only without the ASR permission.
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// Probably Sail should have the cycle CSR even without U-mode but need
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// clarification on spec.
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__asm__ volatile("csrr %0, mcycle" : "=r"(cycles));
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// On Sail, report the number of instructions, the cycle count is
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// meaningless.
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__asm__ volatile("csrr %0, minstret" : "=r"(cycles));
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#else
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__asm__ volatile("rdcycle %0" : "=r"(cycles));
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#endif

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