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1 parent 7fe4579 commit 741a525Copy full SHA for 741a525
llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -210,4 +210,5 @@ def CHERIOT : RISCVProcessorModel<"cheriot",
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FeatureCheri,
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FeatureCapMode,
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FeatureStdExtC,
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- FeatureStdExtM]>;
+ FeatureStdExtM,
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+ FeatureUnalignedScalarMem]>;
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