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[AMDGPU] Remove unused VGPRSingleUseHintInsts feature (llvm#109769)
Fixes SWDEV-498470 (cherry picked from commit 396f677) Change-Id: If965dab720db1a0fe76af6014ae6e57476c0c6d3
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-842
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16 files changed

+5
-842
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llvm/docs/AMDGPUUsage.rst

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -614,9 +614,7 @@ greater than or equal to the version in which the processor was added to the gen
614614
- ``gfx1151``
615615

616616
SALU floating point instructions
617-
and single-use VGPR hint
618-
instructions are not available
619-
on:
617+
are not available on:
620618

621619
- ``gfx1150``
622620
- ``gfx1151``

llvm/lib/Target/AMDGPU/AMDGPU.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -361,9 +361,6 @@ extern char &SIModeRegisterID;
361361
void initializeAMDGPUInsertDelayAluPass(PassRegistry &);
362362
extern char &AMDGPUInsertDelayAluID;
363363

364-
void initializeAMDGPUInsertSingleUseVDSTPass(PassRegistry &);
365-
extern char &AMDGPUInsertSingleUseVDSTID;
366-
367364
void initializeSIInsertHardClausesPass(PassRegistry &);
368365
extern char &SIInsertHardClausesID;
369366

llvm/lib/Target/AMDGPU/AMDGPU.td

Lines changed: 2 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -865,12 +865,6 @@ def FeatureSALUFloatInsts : SubtargetFeature<"salu-float",
865865
"Has SALU floating point instructions"
866866
>;
867867

868-
def FeatureVGPRSingleUseHintInsts : SubtargetFeature<"vgpr-singleuse-hint",
869-
"HasVGPRSingleUseHintInsts",
870-
"true",
871-
"Has single-use VGPR hint instructions"
872-
>;
873-
874868
def FeaturePseudoScalarTrans : SubtargetFeature<"pseudo-scalar-trans",
875869
"HasPseudoScalarTrans",
876870
"true",
@@ -1511,21 +1505,18 @@ def FeatureISAVersion11_0_3 : FeatureSet<
15111505
def FeatureISAVersion11_5_0 : FeatureSet<
15121506
!listconcat(FeatureISAVersion11_Common.Features,
15131507
[FeatureSALUFloatInsts,
1514-
FeatureDPPSrc1SGPR,
1515-
FeatureVGPRSingleUseHintInsts])>;
1508+
FeatureDPPSrc1SGPR])>;
15161509

15171510
def FeatureISAVersion11_5_1 : FeatureSet<
15181511
!listconcat(FeatureISAVersion11_Common.Features,
15191512
[FeatureSALUFloatInsts,
15201513
FeatureDPPSrc1SGPR,
1521-
FeatureVGPRSingleUseHintInsts,
15221514
FeatureGFX11FullVGPRs])>;
15231515

15241516
def FeatureISAVersion11_5_2 : FeatureSet<
15251517
!listconcat(FeatureISAVersion11_Common.Features,
15261518
[FeatureSALUFloatInsts,
1527-
FeatureDPPSrc1SGPR,
1528-
FeatureVGPRSingleUseHintInsts])>;
1519+
FeatureDPPSrc1SGPR])>;
15291520

15301521
def FeatureISAVersion12 : FeatureSet<
15311522
[FeatureGFX12,
@@ -1555,7 +1546,6 @@ def FeatureISAVersion12 : FeatureSet<
15551546
FeatureSALUFloatInsts,
15561547
FeaturePseudoScalarTrans,
15571548
FeatureHasRestrictedSOffset,
1558-
FeatureVGPRSingleUseHintInsts,
15591549
FeatureScalarDwordx3Loads,
15601550
FeatureDPPSrc1SGPR]>;
15611551

@@ -2115,9 +2105,6 @@ def HasNotMADIntraFwdBug : Predicate<"!Subtarget->hasMADIntraFwdBug()">;
21152105
def HasSALUFloatInsts : Predicate<"Subtarget->hasSALUFloatInsts()">,
21162106
AssemblerPredicate<(all_of FeatureSALUFloatInsts)>;
21172107

2118-
def HasVGPRSingleUseHintInsts : Predicate<"Subtarget->hasVGPRSingleUseHintInsts()">,
2119-
AssemblerPredicate<(all_of FeatureVGPRSingleUseHintInsts)>;
2120-
21212108
def HasPseudoScalarTrans : Predicate<"Subtarget->hasPseudoScalarTrans()">,
21222109
AssemblerPredicate<(all_of FeaturePseudoScalarTrans)>;
21232110

llvm/lib/Target/AMDGPU/AMDGPUInsertSingleUseVDST.cpp

Lines changed: 0 additions & 122 deletions
This file was deleted.

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -343,12 +343,6 @@ static cl::opt<bool> EnableSIModeRegisterPass(
343343
cl::init(true),
344344
cl::Hidden);
345345

346-
// Enable GFX11.5+ s_singleuse_vdst insertion
347-
static cl::opt<bool>
348-
EnableInsertSingleUseVDST("amdgpu-enable-single-use-vdst",
349-
cl::desc("Enable s_singleuse_vdst insertion"),
350-
cl::init(false), cl::Hidden);
351-
352346
// Enable GFX11+ s_delay_alu insertion
353347
static cl::opt<bool>
354348
EnableInsertDelayAlu("amdgpu-enable-delay-alu",
@@ -482,7 +476,6 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
482476
initializeAMDGPURewriteUndefForPHILegacyPass(*PR);
483477
initializeAMDGPUUnifyMetadataPass(*PR);
484478
initializeSIAnnotateControlFlowPass(*PR);
485-
initializeAMDGPUInsertSingleUseVDSTPass(*PR);
486479
initializeAMDGPUInsertDelayAluPass(*PR);
487480
initializeSIInsertHardClausesPass(*PR);
488481
initializeSIInsertWaitcntsPass(*PR);
@@ -1624,9 +1617,6 @@ void GCNPassConfig::addPreEmitPass() {
16241617
// cases.
16251618
addPass(&PostRAHazardRecognizerID);
16261619

1627-
if (isPassEnabled(EnableInsertSingleUseVDST, CodeGenOptLevel::Less))
1628-
addPass(&AMDGPUInsertSingleUseVDSTID);
1629-
16301620
if (isPassEnabled(EnableInsertDelayAlu, CodeGenOptLevel::Less))
16311621
addPass(&AMDGPUInsertDelayAluID);
16321622

llvm/lib/Target/AMDGPU/CMakeLists.txt

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,6 @@ add_llvm_target(AMDGPUCodeGen
8181
AMDGPUMacroFusion.cpp
8282
AMDGPUMCInstLower.cpp
8383
AMDGPUIGroupLP.cpp
84-
AMDGPUInsertSingleUseVDST.cpp
8584
AMDGPUMarkLastScratchLoad.cpp
8685
AMDGPUMIRFormatter.cpp
8786
AMDGPUOpenCLEnqueuedBlockLowering.cpp

llvm/lib/Target/AMDGPU/GCNSubtarget.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -206,7 +206,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
206206
bool HasPackedTID = false;
207207
bool ScalarizeGlobal = false;
208208
bool HasSALUFloatInsts = false;
209-
bool HasVGPRSingleUseHintInsts = false;
210209
bool HasPseudoScalarTrans = false;
211210
bool HasRestrictedSOffset = false;
212211

@@ -1210,8 +1209,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
12101209

12111210
bool hasSALUFloatInsts() const { return HasSALUFloatInsts; }
12121211

1213-
bool hasVGPRSingleUseHintInsts() const { return HasVGPRSingleUseHintInsts; }
1214-
12151212
bool hasPseudoScalarTrans() const { return HasPseudoScalarTrans; }
12161213

12171214
bool hasRestrictedSOffset() const { return HasRestrictedSOffset; }

llvm/lib/Target/AMDGPU/SOPInstructions.td

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1716,11 +1716,6 @@ let SubtargetPredicate = isGFX11Plus in {
17161716
"$simm16">;
17171717
} // End SubtargetPredicate = isGFX11Plus
17181718

1719-
let SubtargetPredicate = HasVGPRSingleUseHintInsts in {
1720-
def S_SINGLEUSE_VDST :
1721-
SOPP_Pseudo<"s_singleuse_vdst", (ins s16imm:$simm16), "$simm16">;
1722-
} // End SubtargetPredicate = HasVGPRSingeUseHintInsts
1723-
17241719
let SubtargetPredicate = isGFX12Plus, hasSideEffects = 1 in {
17251720
def S_WAIT_LOADCNT :
17261721
SOPP_Pseudo<"s_wait_loadcnt", (ins s16imm:$simm16), "$simm16",
@@ -2663,12 +2658,6 @@ defm S_ICACHE_INV : SOPP_Real_32_gfx11_gfx12<0x03c>;
26632658

26642659
defm S_BARRIER : SOPP_Real_32_gfx11<0x03d>;
26652660

2666-
//===----------------------------------------------------------------------===//
2667-
// SOPP - GFX1150, GFX12.
2668-
//===----------------------------------------------------------------------===//
2669-
2670-
defm S_SINGLEUSE_VDST : SOPP_Real_32_gfx11_gfx12<0x013>;
2671-
26722661
//===----------------------------------------------------------------------===//
26732662
// SOPP - GFX6, GFX7, GFX8, GFX9, GFX10
26742663
//===----------------------------------------------------------------------===//

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