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1 parent dd8a974 commit f94d08eCopy full SHA for f94d08e
llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -1127,8 +1127,8 @@ void MFMASmallGemmSingleWaveOpt::applyIGLPStrategy(
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unsigned MFMACount = 0;
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unsigned DSRCount = 0;
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- assert((IsPostRA ||
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- DSWCount == DSWWithPermCount == DSWWithSharedVMEMCount == 0) &&
+ assert((IsPostRA || (DSWCount == 0 && DSWWithPermCount == 0 &&
+ DSWWithSharedVMEMCount == 0)) &&
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"DSWCounters should be zero in pre-RA scheduling!");
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SmallVector<SUnit *, 6> DSWithPerms;
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for (auto &SU : DAG->SUnits) {
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