@@ -56,8 +56,6 @@ std::vector<RTLIL::Design*> pushed_designs;
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YOSYS_NAMESPACE_END
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END
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- sed -e ' s,new ezMiniSAT(),nullptr,' -i yosys-src/kernel/register.cc
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-
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YOSYS_PYPI_VER=$( python3 setup.py --version)
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YOSYS_GIT_REV=$( git -C yosys-src rev-parse --short HEAD | tr -d ' \n' )
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YOSYS_VER_STR=' Amaranth Yosys $(YOSYS_VER) ' " (PyPI ver ${YOSYS_PYPI_VER} , git sha1 ${YOSYS_GIT_REV} )"
@@ -72,10 +70,18 @@ kernel/mem.o \
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kernel/ff.o \
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kernel/fmt.o \
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kernel/scopeinfo.o \
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+ kernel/satgen.o \
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+ kernel/qcsat.o \
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kernel/yosys.o \
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libs/bigint/BigInteger.o \
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libs/bigint/BigUnsigned.o \
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libs/sha1/sha1.o \
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+ libs/ezsat/ezsat.o \
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+ libs/ezsat/ezminisat.o \
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+ libs/minisat/Options.o \
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+ libs/minisat/SimpSolver.o \
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+ libs/minisat/Solver.o \
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+ libs/minisat/System.o \
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frontends/ast/ast.o \
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frontends/ast/simplify.o \
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frontends/rtlil/rtlil_parser.tab.o \
@@ -97,7 +103,27 @@ passes/proc/proc_mux.o \
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passes/proc/proc_dlatch.o \
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passes/proc/proc_dff.o \
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passes/proc/proc_rom.o \
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+ passes/opt/opt.o \
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+ passes/opt/opt_merge.o \
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+ passes/opt/opt_mem.o \
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+ passes/opt/opt_mem_feedback.o \
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+ passes/opt/opt_mem_priority.o \
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+ passes/opt/opt_mem_widen.o \
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+ passes/opt/opt_muxtree.o \
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+ passes/opt/opt_reduce.o \
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+ passes/opt/opt_dff.o \
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+ passes/opt/opt_share.o \
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+ passes/opt/opt_clean.o \
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passes/opt/opt_expr.o \
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+ passes/opt/share.o \
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+ passes/opt/wreduce.o \
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+ passes/opt/opt_demorgan.o \
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+ passes/opt/rmports.o \
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+ passes/opt/opt_lut.o \
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+ passes/opt/opt_lut_ins.o \
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+ passes/opt/opt_ffinv.o \
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+ passes/opt/pmux2shiftx.o \
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+ passes/opt/muxpack.o \
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passes/cmds/plugin.o \
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passes/cmds/design_stub.o \
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passes/cmds/select.o \
@@ -108,6 +134,7 @@ passes/techmap/attrmap.o \
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passes/techmap/flatten.o \
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passes/techmap/bmuxmap.o \
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passes/techmap/demuxmap.o \
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+ passes/techmap/simplemap.o \
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backends/rtlil/rtlil_backend.o \
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backends/cxxrtl/cxxrtl_backend.o \
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backends/verilog/verilog_backend.o \
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