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projects/ltc2378: Create HDL design
Signed-off-by: Pop Ioan Daniel <[email protected]>
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‎projects/ltc2378_fmc/Makefile‎

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####################################################################################
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## Copyright (c) 2025 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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include ../scripts/project-toplevel.mk

‎projects/ltc2378_fmc/README.md‎

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# LTC2378-FMC HDL Project
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- Evaluation board product page: TO BE ADDED
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- System documentation: TO BE ADDED
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- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ltc2378_fmc/index.html
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- Evaluation board VADJ: 2.5V
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## Supported parts
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| Part name | Description |
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|-------------------------------------------------|---------------------------------------------------------------------------|
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| [LTC2378-20](https://www.analog.com/ltc2378-20) | 20-Bit, 1-Channel, low noise, low power, high speed (SAR) ADC |
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## Building the project
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Please enter the folder for the FPGA carrier you want to use and read the README.md.

‎projects/ltc2378_fmc/common/ltc2378_bd.tcl‎

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###############################################################################
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## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ltc2378_spi
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create_bd_port -dir O ltc2378_spi_cnv
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create_bd_port -dir I ltc2378_ext_clk
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
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set data_width 32
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set async_spi_clk 1
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set num_cs 1
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set num_sdi 1
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set num_sdo 1
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set sdi_delay 0
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set echo_sclk 0
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set hier_spi_engine spi_ltc2378
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spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
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# activate internal SPI Engine Offload synchronizer
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ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_offload CONFIG.ASYNC_TRIG 1
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# clkgen - 140 MHz
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ad_ip_instance axi_clkgen spi_clkgen
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ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5
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ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
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ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 7
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ad_connect $sys_cpu_clk spi_clkgen/clk
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ad_connect spi_clk spi_clkgen/clk_0
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# pwm generator
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ad_ip_instance axi_pwm_gen ltc2378_trigger_gen
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ad_ip_parameter ltc2378_trigger_gen CONFIG.N_PWMS 2
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ad_ip_parameter ltc2378_trigger_gen CONFIG.PULSE_0_PERIOD 100
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ad_ip_parameter ltc2378_trigger_gen CONFIG.PULSE_0_WIDTH 2
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ad_ip_parameter ltc2378_trigger_gen CONFIG.PULSE_1_PERIOD 100
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ad_ip_parameter ltc2378_trigger_gen CONFIG.PULSE_1_WIDTH 2
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ad_ip_parameter ltc2378_trigger_gen CONFIG.PULSE_1_OFFSET 1
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ad_connect $sys_cpu_clk ltc2378_trigger_gen/s_axi_aclk
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ad_connect sys_cpu_resetn ltc2378_trigger_gen/s_axi_aresetn
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ad_connect ltc2378_ext_clk ltc2378_trigger_gen/ext_clk
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ad_connect ltc2378_spi_cnv ltc2378_trigger_gen/pwm_0
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ad_connect ltc2378_trigger_gen/pwm_1 $hier_spi_engine/${hier_spi_engine}_offload/trigger
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# dma to receive data stream
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ad_ip_instance axi_dmac ltc2378_dma
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ad_ip_parameter ltc2378_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter ltc2378_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter ltc2378_dma CONFIG.CYCLIC 0
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ad_ip_parameter ltc2378_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter ltc2378_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter ltc2378_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter ltc2378_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter ltc2378_dma CONFIG.DMA_DATA_WIDTH_SRC $data_width
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ad_ip_parameter ltc2378_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_connect $sys_cpu_clk $hier_spi_engine/clk
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ad_connect ltc2378_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE
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ad_connect $hier_spi_engine/m_spi ltc2378_spi
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ad_connect spi_clk $hier_spi_engine/spi_clk
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ad_connect sys_cpu_resetn $hier_spi_engine/resetn
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ad_connect spi_clk ltc2378_dma/s_axis_aclk
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ad_connect sys_cpu_resetn ltc2378_dma/m_dest_axi_aresetn
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# AXI address definitions
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ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
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ad_cpu_interconnect 0x44a30000 ltc2378_dma
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ad_cpu_interconnect 0x44a70000 spi_clkgen
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ad_cpu_interconnect 0x44b00000 ltc2378_trigger_gen
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ad_cpu_interrupt "ps-13" "mb-13" ltc2378_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" /$hier_spi_engine/irq
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ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect $sys_cpu_clk ltc2378_dma/m_dest_axi

‎projects/ltc2378_fmc/zed/Makefile‎

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####################################################################################
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## Copyright (c) 2025 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := ltc2378_fmc_zed
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M_DEPS += ../common/ltc2378_bd.tcl
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/zed/zed_system_constr.xdc
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M_DEPS += ../../common/zed/zed_system_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_data_clk.v
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M_DEPS += ../../../library/util_cdc/sync_bits.v
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M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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M_DEPS += ../../../library/common/ad_edge_detect.v
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LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_i2s_adi
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LIB_DEPS += axi_pwm_gen
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += axi_sysid
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LIB_DEPS += spi_engine/axi_spi_engine
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LIB_DEPS += spi_engine/spi_engine_execution
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LIB_DEPS += spi_engine/spi_engine_interconnect
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LIB_DEPS += spi_engine/spi_engine_offload
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LIB_DEPS += sysid_rom
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LIB_DEPS += util_i2c_mixer
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include ../../scripts/project-xilinx.mk

‎projects/ltc2378_fmc/zed/README.md‎

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<!-- no_build_example, no_dts, no_no_os -->
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# LTC2378-FMC/ZED HDL Project
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- VADJ with which it was tested in hardware: 2.5V
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## Building the project
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```
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cd projects/ltc2378_fmc/zed
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make
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```

‎projects/ltc2378_fmc/zed/system_bd.tcl‎

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###############################################################################
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## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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adi_project_files ltc2378_fmc_zed [list \
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"../../../library/common/ad_edge_detect.v" \
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"../../../library/util_cdc/sync_bits.v" \
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]
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# block design
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source ../common/ltc2378_bd.tcl
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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sysid_gen_sys_init_file

‎projects/ltc2378_fmc/zed/system_constr.xdc‎

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###############################################################################
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## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# data interface
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set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ltc2378_spi_sclk]; ## G6 FMC_LA00_CC_P IO_L13P_T2_MRCC_34
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set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ltc2378_spi_sdi]; ## H7 FMC_LA02_P IO_L20P_T3_34
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set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ltc2378_spi_sdo]; ## C11 FMC_LA06_N IO_L10N_T1_34
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set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ltc2378_spi_cnv]; ## D8 FMC_LA01_CC_P IO_L14P_T2_SRCC_34
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set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ltc2378_ext_clk]; ## H4 FMC_CLK0_M2C_P IO_L12P_T1_MRCC_34
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#set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ltc2378_spi_busy]; ## C11 FMC_LA18_CC_P IO_L14P_T2_AD4P_SRCC_35
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set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ltc2378_chain]; ## G7 FMC_LA00_CC_N IO_L13N_T2_MRCC_34
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set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ltc2378_dcgn]; ## D9 FMC_LA01_CC_N IO_L14N_T2_SRCC_34
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# set_property -dict {PACKAGE_PIN #N/A IOSTANDARD LVCMOS25} [get_ports enable]; ## D1 FMC_PG_C2M #N/A
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# external clock, that drives the CNV generator, must have a maximum 100 MHz frequency
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create_clock -period 10.000 -name cnv_ext_clk [get_ports ltc2378_ext_clk]
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# rename auto-generated clock for SPIEngine to spi_clk - 200MHz
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# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk
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create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]
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# relax the SDO path to help closing timing at high frequencies
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set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
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set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
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set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/spi_ltc2378_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
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set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/spi_ltc2378_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]

‎projects/ltc2378_fmc/zed/system_project.tcl‎

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###############################################################################
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## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project ltc23378_fmc_zed
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adi_project_files ltc2378_fmc_zed [list \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \
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"system_top.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
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adi_project_run ltc2378_fmc_zed

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