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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
| 2 | +/* |
| 3 | + * MAX14001/MAX14002 SPI ADC driver |
| 4 | + * |
| 5 | + * Copyright (c) 2025 Marilene Andrade Garcia <[email protected]> |
| 6 | + * |
| 7 | + * Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/MAX14001-MAX14002.pdf |
| 8 | + */ |
| 9 | + |
| 10 | +#include <asm/unaligned.h> |
| 11 | +#include <linux/bitfield.h> |
| 12 | +#include <linux/bitrev.h> |
| 13 | +#include <linux/module.h> |
| 14 | +#include <linux/spi/spi.h> |
| 15 | +#include <linux/iio/iio.h> |
| 16 | +#include <linux/regulator/consumer.h> |
| 17 | + |
| 18 | +/* MAX14001 registers definition */ |
| 19 | +#define MAX14001_REG_ADC 0x00 |
| 20 | +#define MAX14001_REG_FADC 0x01 |
| 21 | +#define MAX14001_REG_FLAGS 0x02 |
| 22 | +#define MAX14001_REG_FLTEN 0x03 |
| 23 | +#define MAX14001_REG_THL 0x04 |
| 24 | +#define MAX14001_REG_THU 0x05 |
| 25 | +#define MAX14001_REG_INRR 0x06 |
| 26 | +#define MAX14001_REG_INRT 0x07 |
| 27 | +#define MAX14001_REG_INRP 0x08 |
| 28 | +#define MAX14001_REG_CFG 0x09 |
| 29 | +#define MAX14001_REG_ENBL 0x0A |
| 30 | +#define MAX14001_REG_ACT 0x0B |
| 31 | +#define MAX14001_REG_WEN 0x0C |
| 32 | + |
| 33 | +/* MAX14001 CONTROL values*/ |
| 34 | +#define MAX14001_REG_WRITE 0x1 |
| 35 | +#define MAX14001_REG_READ 0x0 |
| 36 | + |
| 37 | +/* MAX14001 MASKS */ |
| 38 | +#define MAX14001_MASK_ADDR GENMASK(15, 11) |
| 39 | +#define MAX14001_MASK_WR BIT(10) |
| 40 | +#define MAX14001_MASK_DATA GENMASK(9, 0) |
| 41 | + |
| 42 | +enum max14001_chip_model { |
| 43 | + max14001, |
| 44 | + max14002, |
| 45 | +}; |
| 46 | + |
| 47 | +struct max14001_chip_info { |
| 48 | + const char *name; |
| 49 | +}; |
| 50 | + |
| 51 | +struct max14001_state { |
| 52 | + const struct max14001_chip_info *chip_info; |
| 53 | + struct spi_device *spi; |
| 54 | + int vref_mv; |
| 55 | + |
| 56 | + __be16 rx_buffer __aligned(IIO_DMA_MINALIGN); |
| 57 | + __be16 tx_buffer; |
| 58 | +}; |
| 59 | + |
| 60 | +static struct max14001_chip_info max14001_chip_info_tbl[] = { |
| 61 | + [max14001] = { |
| 62 | + .name = "max14001", |
| 63 | + }, |
| 64 | + [max14002] = { |
| 65 | + .name = "max14002", |
| 66 | + }, |
| 67 | +}; |
| 68 | + |
| 69 | +static int max14001_spi_read(struct max14001_state *st, u16 reg, int *val) |
| 70 | +{ |
| 71 | + struct spi_transfer xfer[] = { |
| 72 | + { |
| 73 | + .tx_buf = &st->tx_buffer, |
| 74 | + .len = sizeof(st->tx_buffer), |
| 75 | + .cs_change = 1, |
| 76 | + }, |
| 77 | + { |
| 78 | + .rx_buf = &st->rx_buffer, |
| 79 | + .len = sizeof(st->rx_buffer), |
| 80 | + }, |
| 81 | + }; |
| 82 | + int ret; |
| 83 | + |
| 84 | + st->tx_buffer = FIELD_PREP(MAX14001_MASK_ADDR, reg) | |
| 85 | + FIELD_PREP(MAX14001_MASK_WR, MAX14001_REG_READ); |
| 86 | + st->tx_buffer = bitrev16(st->tx_buffer); |
| 87 | + |
| 88 | + ret = spi_sync_transfer(st->spi, xfer, ARRAY_SIZE(xfer)); |
| 89 | + if (ret < 0) |
| 90 | + return ret; |
| 91 | + |
| 92 | + st->rx_buffer = bitrev16(be16_to_cpu(st->rx_buffer)); |
| 93 | + *val = FIELD_GET(MAX14001_MASK_DATA, st->rx_buffer); |
| 94 | + |
| 95 | + return 0; |
| 96 | +} |
| 97 | + |
| 98 | +static int max14001_read_raw(struct iio_dev *indio_dev, |
| 99 | + struct iio_chan_spec const *chan, |
| 100 | + int *val, int *val2, long mask) |
| 101 | +{ |
| 102 | + struct max14001_state *st = iio_priv(indio_dev); |
| 103 | + int ret; |
| 104 | + |
| 105 | + switch (mask) { |
| 106 | + case IIO_CHAN_INFO_RAW: |
| 107 | + ret = max14001_spi_read(st, MAX14001_REG_ADC, val); |
| 108 | + if (ret < 0) |
| 109 | + return ret; |
| 110 | + |
| 111 | + return IIO_VAL_INT; |
| 112 | + case IIO_CHAN_INFO_AVERAGE_RAW: |
| 113 | + ret = max14001_spi_read(st, MAX14001_REG_FADC, val); |
| 114 | + if (ret < 0) |
| 115 | + return ret; |
| 116 | + |
| 117 | + return IIO_VAL_INT; |
| 118 | + case IIO_CHAN_INFO_SCALE: |
| 119 | + *val = st->vref_mv; |
| 120 | + *val2 = 10; |
| 121 | + |
| 122 | + return IIO_VAL_FRACTIONAL_LOG2; |
| 123 | + } |
| 124 | + |
| 125 | + return -EINVAL; |
| 126 | +} |
| 127 | + |
| 128 | +static const struct iio_info max14001_info = { |
| 129 | + .read_raw = max14001_read_raw, |
| 130 | +}; |
| 131 | + |
| 132 | +static const struct iio_chan_spec max14001_channel[] = { |
| 133 | + { |
| 134 | + .type = IIO_VOLTAGE, |
| 135 | + .indexed = 1, |
| 136 | + .channel = 0, |
| 137 | + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | |
| 138 | + BIT(IIO_CHAN_INFO_AVERAGE_RAW) | |
| 139 | + BIT(IIO_CHAN_INFO_SCALE), |
| 140 | + } |
| 141 | +}; |
| 142 | + |
| 143 | +static int max14001_probe(struct spi_device *spi) |
| 144 | +{ |
| 145 | + struct device *dev = &spi->dev; |
| 146 | + struct max14001_state *st; |
| 147 | + struct iio_dev *indio_dev; |
| 148 | + int ret; |
| 149 | + |
| 150 | + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); |
| 151 | + if (!indio_dev) |
| 152 | + return -ENOMEM; |
| 153 | + |
| 154 | + st = iio_priv(indio_dev); |
| 155 | + st->spi = spi; |
| 156 | + st->chip_info = spi_get_device_match_data(spi); |
| 157 | + if (!st->chip_info) |
| 158 | + return dev_err_probe(dev, -ENODEV, "Failed to get match data\n"); |
| 159 | + |
| 160 | + indio_dev->name = st->chip_info->name; |
| 161 | + indio_dev->modes = INDIO_DIRECT_MODE; |
| 162 | + indio_dev->info = &max14001_info; |
| 163 | + indio_dev->channels = max14001_channel; |
| 164 | + indio_dev->num_channels = ARRAY_SIZE(max14001_channel); |
| 165 | + |
| 166 | + ret = devm_regulator_get_enable(dev, "vdd"); |
| 167 | + if (ret) |
| 168 | + return dev_err_probe(dev, ret, |
| 169 | + "Failed to enable specified Vdd supply\n"); |
| 170 | + |
| 171 | + ret = devm_regulator_get_enable(dev, "vddl"); |
| 172 | + if (ret) |
| 173 | + return dev_err_probe(dev, ret, |
| 174 | + "Failed to enable specified Vddl supply\n"); |
| 175 | + |
| 176 | + ret = devm_regulator_get_enable_read_voltage(dev, "vrefin"); |
| 177 | + if (ret < 0) |
| 178 | + st->vref_mv = 1250000 / 1000; |
| 179 | + else |
| 180 | + st->vref_mv = ret / 1000; |
| 181 | + |
| 182 | + return devm_iio_device_register(dev, indio_dev); |
| 183 | +} |
| 184 | + |
| 185 | +static const struct spi_device_id max14001_id_table[] = { |
| 186 | + { "max14001", (kernel_ulong_t)&max14001_chip_info_tbl[max14001] }, |
| 187 | + { "max14002", (kernel_ulong_t)&max14001_chip_info_tbl[max14002] }, |
| 188 | + {} |
| 189 | +}; |
| 190 | +MODULE_DEVICE_TABLE(spi, max14001_id_table); |
| 191 | + |
| 192 | +static const struct of_device_id max14001_of_match[] = { |
| 193 | + { .compatible = "adi,max14001", |
| 194 | + .data = &max14001_chip_info_tbl[max14001], }, |
| 195 | + { .compatible = "adi,max14002", |
| 196 | + .data = &max14001_chip_info_tbl[max14002], }, |
| 197 | + { } |
| 198 | +}; |
| 199 | +MODULE_DEVICE_TABLE(of, max14001_of_match); |
| 200 | + |
| 201 | +static struct spi_driver max14001_driver = { |
| 202 | + .driver = { |
| 203 | + .name = "max14001", |
| 204 | + .of_match_table = max14001_of_match, |
| 205 | + }, |
| 206 | + .probe = max14001_probe, |
| 207 | + .id_table = max14001_id_table, |
| 208 | +}; |
| 209 | +module_spi_driver(max14001_driver); |
| 210 | + |
| 211 | +MODULE_AUTHOR( "Marilene Andrade Garcia <[email protected]>"); |
| 212 | +MODULE_DESCRIPTION("Analog Devices MAX14001/MAX14002 ADCs driver"); |
| 213 | +MODULE_LICENSE("GPL"); |
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