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1 parent 93c3a3e commit d7a29e0Copy full SHA for d7a29e0
.github/workflows/test.yaml
@@ -23,9 +23,9 @@ jobs:
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make cocotb-verify-all-rtl
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- name: Check RTL Verification Results
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run: |
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- ls ./verilog/dv/cocotb/sim/*/*/*.log
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- ls ./verilog/dv/cocotb/sim/*/*/simv
+ echo 1
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ls ./verilog/dv/cocotb/sim/*/*/*
+ echo 2
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ls ./verilog/dv/cocotb/sim/*/*-compilation/*
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simv="$GITHUB_WORKSPACE/verilog/dv/cocotb/sim/CI/*-compilation/simv"
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if [ -f $simv ]; then
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