Improve f247 PLL output frequency calculation precision

This will produce the correct result for all integer output frequencies
and a truncated result for all non-integer output frequencies instead of
accumulating an error.

The Hertz(1) * ... / Hertz(1) trick is necessary because the values do
not implement multiplication by each-other so must be coerced into
Hertz. Afterwards, if they remain as Hertz the final division becomes
Hertz / Hertz i.e. u32 which is not what we want. So dividing by Hertz
early ensures the final division becomes Hertz / u32 which is just
Hertz.

Unfortunately, avoiding this trickery is non-trivial. I believe this may
be the cleanest solution.

Author: EliteTK

embassy-stm32/CHANGELOG.md

@@ -15,6 +15,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Add I2S support for STM32F1, STM32C0, STM32F0, STM32F3, STM32F7, STM32G0, STM32WL, STM32H5, STM32H7RS
 - fix: STM32: Prevent dropped DacChannel from disabling Dac peripheral if another DacChannel is still in scope ([#4577](https://github.com/embassy-rs/embassy/pull/4577))
 - feat: Added support for more OctoSPI configurations (e.g. APS6408 RAM) ([#4581](https://github.com/embassy-rs/embassy/pull/4581))
+- Improve the PLL output frequency calculation precision for the F2, F4, and F7
+  series.
 
 ## 0.4.0 - 2025-08-26
 

embassy-stm32/src/rcc/f247.rs

@@ -393,7 +393,8 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
 
     let in_freq = pll_src / pll.prediv;
     assert!(max::PLL_IN.contains(&in_freq));
-    let vco_freq = in_freq * pll.mul;
+    let pll_mulsrc = pll_src * pll.mul;
+    let vco_freq = pll_mulsrc / pll.prediv;
     assert!(max::PLL_VCO.contains(&vco_freq));
 
     // stm32f2 plls are like swiss cheese
@@ -408,9 +409,15 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
         }
     }
 
-    let p = pll.divp.map(|div| vco_freq / div);
-    let q = pll.divq.map(|div| vco_freq / div);
-    let r = pll.divr.map(|div| vco_freq / div);
+    let p = pll
+        .divp
+        .map(|div| pll_mulsrc / (Hertz(1) * pll.prediv * div / Hertz(1)));
+    let q = pll
+        .divq
+        .map(|div| pll_mulsrc / (Hertz(1) * pll.prediv * div / Hertz(1)));
+    let r = pll
+        .divr
+        .map(|div| pll_mulsrc / (Hertz(1) * pll.prediv * div / Hertz(1)));
 
     macro_rules! write_fields {
         ($w:ident) => {