Merge pull request #36 from enclustra/feature/width-check

Add VHDL width checks

Author: harry-commin-enclustra

Changelog.md

@@ -1,3 +1,9 @@
+## 2.3.0
+* Features
+  * Added support for NVC simulator.
+  * Added support for Questa 3-step flow.
+  * Added width checks to VHDL to ensure data width matches format (#33).
+
 ## 2.2.1
 * Bugfixes
   * Added workaround for Efinity and Gowin EDA bugs in ieee.math_real."mod".

README.md

@@ -16,10 +16,10 @@ The currently supported langauges are:
 
 <sup>\*</sup>All RTL code is VHDL-93 compliant (for maximum compatibility with synthesis toolchains). Testbenches are VHDL-2008 compliant.
 
-SystemVerilog support is under active development in 2024. However, weak toolchain support for SystemVerilog is proving to be a significant barrier.
-
 C++ support will be added if sufficient demand arises. An experimental partial implementation (based on [GMP](https://gmplib.org/)) gave good results.
 
+SystemVerilog support was investigated in 2024. However, weak toolchain support for SystemVerilog is proving to be a significant barrier.
+
 ### Usage Examples
 
 High-level usage examples can be found, for example, in the open-source [psi_fix](https://github.com/paulscherrerinstitute/psi_fix) library, which internally uses *en\_cl\_fix* for its fixed-point arithmetic.
@@ -46,7 +46,7 @@ See [Changelog](Changelog.md).
 - Python 3 (tested with >= 3.10)
 - Python packages
     - *numpy* (tested with >= 1.24.3)
-    - *vunit-hdl* (tested with >= 4.7.0)
+    - *vunit-hdl* (tested with >= 5.0.0.dev6)
 
 The required Python packages can be installed as follows:
 
@@ -62,7 +62,7 @@ Tested with MATLAB R2023b, and others.
 
 All modern VHDL simulators supported by [VUnit](https://vunit.github.io/) should work.
 
-Tested with: GHDL 4.1.0, Modelsim ASE 2020.1, Modelsim AE 2020.1, Modelsim ME 2022.2, Modelsim PE 2024.1, Questa FE 2023.4, and others.
+Tested with: GHDL 4.1.0, NVC 1.17.1, Modelsim ASE 2020.1, Modelsim AE 2020.1, Modelsim ME 2022.2, Modelsim PE 2024.1, Questa FE 2023.4, and others.
 
 ## Fixed-Point Number Representation
 
@@ -194,6 +194,7 @@ If warnings are enabled, then the HDL simulator or software environment will iss
 - MATLAB tests can be found in ./bittrue/tests/matlab/.
 - VHDL testbenches can be found in ./tb/ and are executed from the ./sim/ directory. Any modern simulator supported by [VUnit](https://vunit.github.io/) (see [Dependencies](#dependencies)) should work. Some examples:
     - GHDL example: `python run.py --simulator=ghdl --simulator-path='C:/msys64/mingw64/bin'`
+    - NVC example: `python run.py --simulator=nvc --simulator-path='C:/Program Files/nvc/bin'`
     - Modelsim ASE example: `python run.py --simulator=modelsim --simulator-path='C:/intelFPGA/20.1/modelsim_ase/win32aloem'`
     - Modelsim AE example: `python run.py --simulator=modelsim --simulator-path='C:/intelFPGA/20.1/modelsim_ae/win32aloem'`
     - Modelsim ME example: `python run.py --simulator=modelsim --simulator-path='C:/Microchip/Libero_SoC_v2022.2/ModelSimPro/win32acoem'`

hdl/en_cl_fix_pkg.vhd

@@ -328,7 +328,7 @@ package body en_cl_fix_pkg is
 
     function convert(a : std_logic_vector; aFmt, rFmt : FixFormat_t) return std_logic_vector is
         -- Force downto 0
-        constant a_c    : std_logic_vector(a'length-1 downto 0) := a;
+        constant a_c    : std_logic_vector(cl_fix_width(aFmt)-1 downto 0) := a;
 
         -- This function converts from aFmt to rFmt without any rounding or saturation:
         --     - It does *not* support rFmt.F < aFmt.F (offset_c is type natural). To reduce frac
@@ -915,7 +915,7 @@ package body en_cl_fix_pkg is
         fmt_check   : boolean := true
     ) return std_logic_vector is
         -- Force downto 0
-        constant a_c            : std_logic_vector(a'length-1 downto 0) := a;
+        constant a_c            : std_logic_vector(cl_fix_width(a_fmt)-1 downto 0) := a;
 
         -- The result format takes care of potential integer growth due to the rounding mode.
         -- In the intermediate calculation, we need to +/- up to 2.0**-(result_fmt.F+1) in order to
@@ -1221,8 +1221,8 @@ package body en_cl_fix_pkg is
         saturate    : FixSaturate_t := Warn_s
     ) return std_logic_vector is
         -- Force downto 0
-        constant a_c            : std_logic_vector(a'length-1 downto 0) := a;
-        constant b_c            : std_logic_vector(b'length-1 downto 0) := b;
+        constant a_c            : std_logic_vector(cl_fix_width(a_fmt)-1 downto 0) := a;
+        constant b_c            : std_logic_vector(cl_fix_width(b_fmt)-1 downto 0) := b;
 
         -- VHDL doesn't define a * operator for mixed signed*unsigned or unsigned*signed.
         -- Just inside cl_fix_mult, it is safe to define them for local use.
@@ -1314,7 +1314,7 @@ package body en_cl_fix_pkg is
 
     function cl_fix_sign(a : std_logic_vector; aFmt : FixFormat_t) return std_logic is
         -- Force downto 0
-        constant a_c    : std_logic_vector(a'length-1 downto 0) := a;
+        constant a_c    : std_logic_vector(cl_fix_width(aFmt)-1 downto 0) := a;
     begin
         if aFmt.S = 0 or cl_fix_width(aFmt) = 0 then
             return '0';

requirements.txt

@@ -1,2 +1,2 @@
-numpy==1.24.3
-vunit-hdl==4.7.0
+numpy==2.3.2
+vunit-hdl==5.0.0.dev6

sim/common.py

@@ -22,19 +22,16 @@
 from os import environ, system, getcwd, chdir
 
 # Import VUnit
-try:
-    import sys
-    sys.path.append(join(abspath(dirname(__file__)), "../../vunit"))
-    import VUnitCLI, VUnit
-except ImportError as e:
-    from vunit import VUnitCLI, VUnit
+import sys
+sys.path.insert(1, abspath(dirname(__file__)) + "/../../lib/FW/VHDL/vunit")
+from vunit import VUnitCLI, VUnit
 
 # Add custom command line arguments
 cli = VUnitCLI()
 cli.parser.add_argument(
         "--simulator",
         default=environ["EN_SIM_NAME"] if "EN_SIM_NAME" in environ else None,
-        help="Define simulator to be used: name (allowed values: modelsim, questa or ghdl)",
+        help="Define simulator to be used: name (allowed values: modelsim, questa, nvc or ghdl)",
     )
 cli.parser.add_argument(
         "-s",
@@ -54,11 +51,6 @@
         default=False,
         help="Enables simulation coverage",
     )
-cli.parser.add_argument(
-    "--vivado-dir",
-    default=environ["EN_VIVADO_BIN"] if "EN_VIVADO_BIN" in environ else None,
-    help="Path to the Vivado install folder",
-    )
 cli.parser.add_argument(
         "--disable-cosim",
         action="store_true",
@@ -71,7 +63,7 @@
 
 # Check arguments
 if args.simulator == None:
-    raise Exception("\n\nERROR: please use --simulator <name> to define the simulator. Allowed values: modelsim or ghdl. E.g: python run.py --simulator modelsim\n")
+    raise Exception("\n\nERROR: please use --simulator <name> to define the simulator. Allowed values: modelsim, questa, nvc or ghdl. E.g: python run.py --simulator modelsim\n")
 if args.simulator_path == None:
     raise Exception("\n\nERROR: please use --simulator-path <path> to define the simulator path. E.g.: python run.py --simulator-path E:/modeltech_pe_2020.1/win32pe\n")
 
@@ -84,27 +76,33 @@
     environ["VUNIT_SIMULATOR"] = args.simulator
 environ["VUNIT_MODELSIM_PATH"] = args.simulator_path
 environ["VUNIT_GHDL_PATH"] = args.simulator_path
+environ["VUNIT_NVC_PATH"] = args.simulator_path
 
 # Set VHDL standard according to the simulators
 if args.simulator == 'modelsim' or args.simulator == 'questa':
     vhdl_standard_rtl = "93"
     vhdl_standard_tb  = "2008"
-elif args.simulator == 'ghdl':
+elif args.simulator == 'ghdl' or args.simulator == 'nvc':
     vhdl_standard_rtl = "2008"
     vhdl_standard_tb  = "2008"
 else:
-    raise Exception("\n\nERROR: please use --simulator <name> to define the simulator. Allowed values: modelsim, questa or ghdl. E.g: python run.py --simulator modelsim\n")
+    raise Exception("\n\nERROR: please use --simulator <name> to define the simulator. Allowed values: modelsim, questa, nvc or ghdl. E.g: python run.py --simulator modelsim\n")
 
 # Callback function which is called after running tests (merge coverage data)
 def post_run(results):
     if args.coverage:
-        root = dirname(__file__)
-        coverage_data = join(root, "coverage/coverage_data.ucdb")
-        coverage_do = join(root, "coverage/coverage.do")
-        cwd = getcwd()
-        chdir(root)
-        results.merge_coverage(file_name=coverage_data)
-        print("generating coverage report file...")
-        system('%s/vsim -c -viewcov %s -do %s' % (environ["VUNIT_MODELSIM_PATH"], coverage_data, coverage_do))
-        print("done creating coverage report file.")
-        chdir(cwd)
+        if args.simulator in ['questa', 'modelsim']:
+            root = dirname(__file__)
+            coverage_data = join(root, 'coverage/coverage_data.ucdb')
+            coverage_do = join(root, 'coverage/coverage.do')
+            cwd = getcwd()
+            chdir(root)
+            results.merge_coverage(file_name=coverage_data)
+            print('generating coverage report file...')
+            system('%s/vsim -c -viewcov %s -do %s' % (environ['VUNIT_MODELSIM_PATH'], coverage_data, coverage_do))
+            print('done creating coverage report file.')
+            chdir(cwd)
+        elif args.simulator == 'nvc':
+            print("----------------------------------------------------------")
+            print("Warning: Coverage support with 'nvc' is not yet supported.")
+            print("----------------------------------------------------------")

sim/run.py

@@ -204,17 +204,34 @@ def __init__(self, dirname):
     # Set compile and simulation options
     ###############################################################################################
 
-    # Set compile and simulation options
-    lib.set_compile_option("modelsim.vcom_flags", ["+cover=sbceft", "-suppress", "143,14408"])
+    # Set compile and simulation options for GHDL
+    vu.add_compile_option("ghdl.a_flags", ["--warn-no-hide"])
+    lib.set_compile_option("ghdl.a_flags", ["-frelaxed", "--warn-no-hide", "--warn-no-specs"])
+    lib.set_sim_option("ghdl.elab_flags", ["-frelaxed"])
+    lib.set_sim_option("ghdl.sim_flags", ["--max-stack-alloc=0"])
+
+    # Set compile and simulation options for NVC
+    vu.add_compile_option("nvc.a_flags", ["--relaxed", "--check-synthesis"])
+    lib.set_sim_option("nvc.global_flags", ["-M 8192m"])
+    lib.set_sim_option("nvc.heap_size", "8192m")
+
+    # Set compile and simulation options for Modelsim and Questa
+    lib.set_compile_option("modelsim.vcom_flags", ["+cover=sbceft", "-check_synthesis", "-coverdeglitch", "0", "-suppress", "143"])
     lib.set_compile_option("modelsim.vlog_flags", ["+cover=sbceft"])
     lib.set_sim_option("modelsim.vsim_flags", ["-t 1ps", "-voptargs=+acc"])
+    if args.simulator == 'questa' and args.gui == False:
+        lib.set_sim_option("modelsim.three_step_flow", True)
+
+    # Set compile and simulation options for all simulators
     lib.set_sim_option("disable_ieee_warnings", True)
     if args.coverage:
         lib.set_sim_option("enable_coverage", True)
 
     # Add waveform automatically when running in GUI mode.
     for tb in lib.get_test_benches():
         tb.set_sim_option("modelsim.init_file.gui", join(root, "scripts/" + tb.name + "_wave.do"))
+        tb.set_sim_option("ghdl.viewer_script.gui", join(root, "scripts/" + tb.name + "_wave.cmd"))
+        tb.set_sim_option("nvc.viewer_script.gui", join(root, "scripts/" + tb.name + "_wave.cmd"))
 
 if __name__ == '__main__':