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[llvm] Proofread AArch64SME.rst (#155137)
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llvm/docs/AArch64SME.rst

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@@ -18,8 +18,8 @@ This document describes how the SME ACLE attributes map to LLVM IR
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attributes and how LLVM lowers these attributes to implement the rules and
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requirements of the ABI.
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Below we describe the LLVM IR attributes and their relation to the C/C++
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level ACLE attributes:
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Below, we describe the LLVM IR attributes and their relation to the
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C/C++-level ACLE attributes:
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``aarch64_pstate_sm_enabled``
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is used for functions with ``__arm_streaming``
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Clang must ensure that the above attributes are added both to the
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function's declaration/definition as well as to their call-sites. This is
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important for calls to attributed function pointers, where there is no
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definition or declaration available.
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important for calls to attributed function pointers, where no
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definition or declaration is available.
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2. Handling PSTATE.SM
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``vscale`` does not. If we let the compiler insert the appropriate ``smstart``
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and ``smstop`` instructions around call boundaries, then the effects on SVE
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state can be mitigated. By limiting the state changes to a very brief window
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around the call we can control how the operations are scheduled and how live
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around the call, we can control how the operations are scheduled and how live
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values remain preserved between state transitions.
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In order to control PSTATE.SM at this level of granularity, we use function and
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* It is undefined behaviour to pass or return (pointers to) scalable vector
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objects to/from functions which may use a different SVE vector length.
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This includes functions with a non-streaming interface, but marked with
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This includes functions with a non-streaming interface but marked with
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``aarch64_pstate_sm_body``.
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* It is not allowed for a function to be decorated with both
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``aarch64_new_za``, ``aarch64_in_za``, ``aarch64_out_za``, ``aarch64_inout_za``,
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``aarch64_preserves_za``.
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These restrictions also apply in the higher level SME ACLE, which means we can
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These restrictions also apply in the higher-level SME ACLE, which means we can
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emit diagnostics in Clang to signal users about incorrect behaviour.
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When ``CurrentState`` and ``ExpectedState`` can be evaluated at compile-time
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(i.e. they are both constants) then an unconditional ``smstart/smstop``
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instruction is emitted. Otherwise the node is matched to a Pseudo instruction
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instruction is emitted. Otherwise, the node is matched to a Pseudo instruction
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which expands to a compare/branch and a ``smstart/smstop``. This is necessary to
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implement transitions from ``SC -> N`` and ``SC -> S``.
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insert a SMSTOP after the call.
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If the function that is called is an intrinsic with no side-effects which in
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turn is lowered to a function call (e.g. ``@llvm.cos()``), then the call to
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turn is lowered to a function call (e.g., ``@llvm.cos()``), then the call to
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``@llvm.cos()`` is not part of any Chain; it can be scheduled freely.
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Lowering of a Callsite creates a small chain of nodes which:
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can use the streaming vector-length to allocate the stack-slots through the
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``ADDSVL`` instruction, even when the CPU is not yet in streaming mode.
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This only works for locals and not callee-save slots, since LLVM doesn't support
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This works only for locals and not callee-save slots, since LLVM doesn't support
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mixing two different scalable vector lengths in one stack frame. That means that the
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case where a function is marked ``arm_locally_streaming`` and needs to spill SVE
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callee-saves in the prologue is currently unsupported. However, it is unlikely
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for this to happen without user intervention, because ``arm_locally_streaming``
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for this to happen without user intervention because ``arm_locally_streaming``
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functions cannot take or return vector-length-dependent values. This would otherwise
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require forcing both the SVE PCS using '``aarch64_sve_pcs``' combined with using
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``arm_locally_streaming`` in order to encounter this problem. This combination
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return array[N - 1] + arg;
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}
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should use ADDSVL for allocating the stack space and should avoid clobbering
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should use ``ADDSVL`` for allocating the stack space and should avoid clobbering
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the return/argument values.
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.. code-block:: none
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* When executing a program in normal mode (PSTATE.SM=0), a subset of SME
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instructions are invalid.
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* Streaming-compatible functions must only use instructions that are valid when
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* Streaming-compatible functions must use only instructions that are valid when
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either PSTATE.SM=0 or PSTATE.SM=1.
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The value of PSTATE.SM is not controlled by the feature flags, but rather by the
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function attributes. This means that we can compile for '``+sme``' and the compiler
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function attributes. This means that we can compile for '``+sme``', and the compiler
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will code-generate any instructions, even if they are not legal under the requested
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streaming mode. The compiler needs to use the function attributes to ensure the
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compiler doesn't do transformations under the assumption that certain operations
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are available at runtime.
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We made a conscious choice not to model this with feature flags, because we
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We made a conscious choice not to model this with feature flags because we
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still want to support inline-asm in either mode (with the user placing
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smstart/smstop manually), and this became rather complicated to implement at the
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individual instruction level (see `D120261 <https://reviews.llvm.org/D120261>`_
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requires changes to the CostModel, Legalization and SelectionDAG lowering.
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We will also emit diagnostics in Clang to prevent the use of
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non-streaming(-compatible) operations, e.g. through ACLE intrinsics, when a
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non-streaming(-compatible) operations, e.g., through ACLE intrinsics, when a
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function is decorated with the streaming mode attributes.
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:Overview:
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The predicate-as-counter type represents the type of a predicate-as-counter
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value held in a AArch64 SVE predicate register. Such a value contains
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value held in an AArch64 SVE predicate register. Such a value contains
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information about the number of active lanes, the element width and a bit that
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tells whether the generated mask should be inverted. ACLE intrinsics should be
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used to move the predicate-as-counter value to/from a predicate vector.

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