Revise as proposed comments, including

- Fix macros in assembler_riscv_c.hpp
- Remove UncompressibleRegion
- Modify comments
- Change names: C-Ext to RVC

Author: zhengxiaolinX

src/hotspot/cpu/riscv/assembler_riscv_c.hpp

@@ -23,8 +23,8 @@
  *
  */
 
-#ifndef CPU_RISCV_ASSEMBLER_RISCV_CEXT_HPP
-#define CPU_RISCV_ASSEMBLER_RISCV_CEXT_HPP
+#ifndef CPU_RISCV_ASSEMBLER_RISCV_C_HPP
+#define CPU_RISCV_ASSEMBLER_RISCV_C_HPP
 
 private:
   bool _in_compressible_region;
@@ -33,7 +33,7 @@
   void set_in_compressible_region(bool b) { _in_compressible_region = b; }
 public:
 
-  // C-Ext: If an instruction is compressible, then
+  // RVC: If an instruction is compressible, then
   //   we will implicitly emit a 16-bit compressed instruction instead of the 32-bit
   //   instruction in Assembler. All below logic follows Chapter -
   //   "C" Standard Extension for Compressed Instructions, Version 2.0.
@@ -43,27 +43,20 @@
   // Note:
   //   1. When UseRVC is enabled, 32-bit instructions under 'CompressibleRegion's will be
   //      transformed to 16-bit instructions if compressible.
-  //   2. C-Ext's instructions in Assembler always begin with 'c_' prefix, as 'c_li',
+  //   2. RVC instructions in Assembler always begin with 'c_' prefix, as 'c_li',
   //      but most of time we have no need to explicitly use these instructions.
-  //   3. In some cases, we need to force using one instruction's uncompressed version,
-  //      for instance code being patched should remain its general and longest version
-  //      to cover all possible cases, or code requiring a fixed length.
-  //      So we introduce 'UncompressibleRegion' to force instructions in its range
-  //      to remain its normal 4-byte version.
+  //   3. We introduce 'CompressibleRegion' to hint instructions in this Region's RTTI range
+  //      are qualified to change to their 2-byte versions.
   //      An example:
   //
   //        CompressibleRegion cr(_masm);
-  //        __ andr(...);      // this instruction could change to c.and if qualified
-  //        {
-  //          UncompressibleRegion ur(_masm);
-  //          __ andr(...);    // this instruction would remain the normal 32-bit form of andr
-  //        }
+  //        __ andr(...);      // this instruction could change to c.and if able to
   //
-  //   4. Using -XX:PrintAssemblyOptions=no-aliases could print C-Ext instructions instead of
+  //   4. Using -XX:PrintAssemblyOptions=no-aliases could print RVC instructions instead of
   //      normal ones.
   //
 
-  // C-Ext: extract a 16-bit instruction.
+  // RVC: extract a 16-bit instruction.
   static inline uint16_t c_extract(uint16_t val, unsigned msb, unsigned lsb) {
     assert_cond(msb >= lsb && msb <= 15);
     unsigned nbits = msb - lsb + 1;
@@ -80,7 +73,7 @@
     return result;
   }
 
-  // C-Ext: patch a 16-bit instruction.
+  // RVC: patch a 16-bit instruction.
   static void c_patch(address a, unsigned msb, unsigned lsb, uint16_t val) {
     assert_cond(a != NULL);
     assert_cond(msb >= lsb && msb <= 15);
@@ -99,31 +92,31 @@
     c_patch(a, bit, bit, val);
   }
 
-  // C-Ext: patch a 16-bit instruction with a general purpose register ranging [0, 31] (5 bits)
+  // RVC: patch a 16-bit instruction with a general purpose register ranging [0, 31] (5 bits)
   static void c_patch_reg(address a, unsigned lsb, Register reg) {
     c_patch(a, lsb + 4, lsb, reg->encoding_nocheck());
   }
 
-  // C-Ext: patch a 16-bit instruction with a general purpose register ranging [8, 15] (3 bits)
+  // RVC: patch a 16-bit instruction with a general purpose register ranging [8, 15] (3 bits)
   static void c_patch_compressed_reg(address a, unsigned lsb, Register reg) {
     c_patch(a, lsb + 2, lsb, reg->compressed_encoding_nocheck());
   }
 
-  // C-Ext: patch a 16-bit instruction with a float register ranging [0, 31] (5 bits)
+  // RVC: patch a 16-bit instruction with a float register ranging [0, 31] (5 bits)
   static void c_patch_reg(address a, unsigned lsb, FloatRegister reg) {
     c_patch(a, lsb + 4, lsb, reg->encoding_nocheck());
   }
 
-  // C-Ext: patch a 16-bit instruction with a float register ranging [8, 15] (3 bits)
+  // RVC: patch a 16-bit instruction with a float register ranging [8, 15] (3 bits)
   static void c_patch_compressed_reg(address a, unsigned lsb, FloatRegister reg) {
     c_patch(a, lsb + 2, lsb, reg->compressed_encoding_nocheck());
   }
 
 public:
 
-// C-Ext: Compressed Instructions
+// RVC: Compressed Instructions
 
-// --------------  C-Ext Instruction Definitions  --------------
+// --------------  RVC Instruction Definitions  --------------
 
   void c_nop() {
     c_addi(x0, 0);
@@ -545,13 +538,13 @@
 
 #undef INSN
 
-// --------------  C-Ext Transformation Macros  --------------
+// --------------  RVC Transformation Macros  --------------
 
-// two C-Ext macros
+// two RVC macros
 #define COMPRESSIBLE          true
 #define NOT_COMPRESSIBLE      false
 
-// a pivotal dispatcher for C-Ext
+// a pivotal dispatcher for RVC
 #define EMIT_MAY_COMPRESS(C, NAME, ...)               EMIT_MAY_COMPRESS_##C(NAME, __VA_ARGS__)
 #define EMIT_MAY_COMPRESS_true(NAME, ...)             EMIT_MAY_COMPRESS_##NAME(__VA_ARGS__)
 #define EMIT_MAY_COMPRESS_false(NAME, ...)
@@ -560,7 +553,7 @@
 #define CHECK_CEXT_AND_COMPRESSIBLE(...)              IS_COMPRESSIBLE(UseRVC && in_compressible_region() && __VA_ARGS__)
 #define CHECK_CEXT()                                  if (UseRVC && in_compressible_region())
 
-// C-Ext transformation macros
+// RVC transformation macros
 #define EMIT_RVC_cond(PREFIX, COND, EMIT) {                                            \
     PREFIX                                                                             \
     CHECK_CEXT_AND_COMPRESSIBLE(COND) {                                                \
@@ -869,36 +862,20 @@
 // --------------------------
 
 public:
-// C-Ext: an abstact compressible region
-class AbstractCompressibleRegion : public StackObj {
+// RVC: a compressible region
+class CompressibleRegion : public StackObj {
 protected:
   Assembler *_masm;
   bool _prev_in_compressible_region;
-protected:
-  AbstractCompressibleRegion(Assembler *_masm)
-  : _masm(_masm)
-  , _prev_in_compressible_region(_masm->in_compressible_region()) {}
-};
-
-class CompressibleRegion : public AbstractCompressibleRegion {
 public:
-  CompressibleRegion(Assembler *_masm) : AbstractCompressibleRegion(_masm) {
+  CompressibleRegion(Assembler *_masm)
+  : _masm(_masm)
+  , _prev_in_compressible_region(_masm->in_compressible_region()) {
     _masm->set_in_compressible_region(true);
   }
   ~CompressibleRegion() {
     _masm->set_in_compressible_region(_prev_in_compressible_region);
   }
 };
 
-// C-Ext: an uncompressible region
-class UncompressibleRegion : public AbstractCompressibleRegion {
-public:
-  UncompressibleRegion(Assembler *_masm) : AbstractCompressibleRegion(_masm) {
-    _masm->set_in_compressible_region(false);
-  }
-  ~UncompressibleRegion() {
-    _masm->set_in_compressible_region(_prev_in_compressible_region);
-  }
-};
-
-#endif // CPU_RISCV_ASSEMBLER_RISCV_CEXT_HPP
+#endif // CPU_RISCV_ASSEMBLER_RISCV_C_HPP

src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp

@@ -1323,7 +1323,7 @@ void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Op
 }
 
 void LIR_Assembler::align_call(LIR_Code code) {
-  // C-Ext: With C-Ext a call may get 2-byte aligned.
+  // RVC: With RVC a call may get 2-byte aligned.
   //   the address of jal itself (which will be patched later) should not span the cache line.
   //   See CallDynamicJavaDirectNode::compute_padding() for more info.
   __ align(4);

src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp

@@ -240,7 +240,7 @@ void BarrierSetAssembler::nmethod_entry_barrier(MacroAssembler* masm) {
     return;
   }
 
-  // C-Ext: RISCV's amoswap instructions need an alignment for the memory address it swaps
+  // RVC: RISCV's amoswap instructions need an alignment for the memory address it swaps
   //   when we reach here we may get a 2-byte alignment so need to align it
   __ align(4, nmethod_barrier_guard_offset());
 

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp

@@ -2926,7 +2926,7 @@ address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
 
   // make sure 4 byte aligned here, so that the destination address would be
   // 8 byte aligned after 3 intructions
-  // C-Ext: when we reach here we may get a 2-byte alignment so need to align it
+  // RVC: when we reach here we may get a 2-byte alignment so need to align it
   align(wordSize, NativeCallTrampolineStub::data_offset);
 
   relocate(trampoline_stub_Relocation::spec(code()->insts()->start() +

src/hotspot/cpu/riscv/register_riscv.hpp

@@ -60,7 +60,7 @@ class RegisterImpl: public AbstractRegisterImpl {
     number_of_byte_registers = 32,
     max_slots_per_register   = 2,
 
-    // C-Ext: integer registers in the range of [x8~x15] are correspond for RVC. Please see Table 16.2 in spec.
+    // RVC: integer registers in the range of [x8~x15] correspond to RVC. Please see Table 16.2 in spec.
     compressed_register_base = 8,
     compressed_register_top  = 15,
   };
@@ -140,7 +140,7 @@ class FloatRegisterImpl: public AbstractRegisterImpl {
     number_of_registers     = 32,
     max_slots_per_register  = 2,
 
-    // C-Ext: float registers in the range of [f8~f15] are correspond for RVC. Please see Table 16.2 in spec.
+    // RVC: float registers in the range of [f8~f15] correspond to RVC. Please see Table 16.2 in spec.
     compressed_register_base = 8,
     compressed_register_top  = 15,
   };

src/hotspot/cpu/riscv/riscv.ad

@@ -1190,7 +1190,7 @@ int MachCallNativeNode::ret_addr_offset() {
   return -1;
 }
 
-// C-Ext: With C-Ext a call may get 2-byte aligned.
+// RVC: With RVC a call may get 2-byte aligned.
 //   The offset encoding in jal ranges bits [12, 31], which could span the cache line.
 //   Patching this unaligned address will make the write operation not atomic.
 //   Other threads may be running the same piece of code at full speed, causing concurrency issues.
@@ -1201,7 +1201,7 @@ int CallStaticJavaDirectNode::compute_padding(int current_offset) const
   return align_up(current_offset, alignment_required()) - current_offset;
 }
 
-// C-Ext: With C-Ext a call may get 2-byte aligned.
+// RVC: With RVC a call may get 2-byte aligned.
 //   The offset encoding in jal ranges bits [12, 31], which could span the cache line.
 //   Patching this unaligned address will make the write operation not atomic.
 //   Other threads may be running the same piece of code at full speed, causing concurrency issues.
@@ -1210,7 +1210,7 @@ int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
 {
   // skip the movptr in MacroAssembler::ic_call():
   // lui + addi + slli + addi + slli + addi
-  // Though movptr() has already 4-byte aligned with or without C-Ext,
+  // Though movptr() has already 4-byte aligned with or without RVC,
   // We need to prevent from further changes by explicitly calculating the size.
   const int movptr_size = 6 * NativeInstruction::instruction_size;
   current_offset += movptr_size;
@@ -1246,7 +1246,7 @@ uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 
   void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
     C2_MacroAssembler _masm(&cbuf);
-    Assembler::CompressibleRegion cr(&_masm);
+    Assembler::CompressibleRegion cr(&_masm); // RVC: nops shall be 2-byte under RVC for alignment purposes.
     for (int i = 0; i < _count; i++) {
       __ nop();
     }