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refactor: disable all interrupts outside of inner impls
1 parent e2c81cf commit 3403c68

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+4
-12
lines changed

1 file changed

+4
-12
lines changed

drv/stm32h7-qspi/src/lib.rs

Lines changed: 4 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -233,9 +233,8 @@ impl Qspi {
233233
data: &[u8],
234234
) -> Result<(), QspiError> {
235235
let result = self.write_impl_inner(command, addr, data);
236-
if result.is_err() {
237-
self.disable_all_interrupts();
238-
}
236+
// Clean up by disabling our interrupt sources.
237+
self.disable_all_interrupts();
239238
result
240239
}
241240

@@ -327,9 +326,6 @@ impl Qspi {
327326
// We're now interested in transfer complete, not FIFO ready.
328327
self.wait_for_transfer_complete();
329328

330-
// Clean up by disabling our interrupt sources.
331-
self.disable_all_interrupts();
332-
333329
Ok(())
334330
}
335331

@@ -340,9 +336,8 @@ impl Qspi {
340336
out: &mut [u8],
341337
) -> Result<(), QspiError> {
342338
let result = self.read_impl_inner(command, addr, out);
343-
if result.is_err() {
344-
self.disable_all_interrupts();
345-
}
339+
// Clean up by disabling our interrupt sources.
340+
self.disable_all_interrupts();
346341
result
347342
}
348343

@@ -453,9 +448,6 @@ impl Qspi {
453448
// set, it appears.
454449
self.wait_for_transfer_complete();
455450

456-
// Clean up by disabling our interrupt sources.
457-
self.disable_all_interrupts();
458-
459451
Ok(())
460452
}
461453

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