Use quad read command for QSPI

We aren't actually making use of all 4 lines on the QSPI chip.
Use the appropriate command to get a nice performance improvement.
It does come at the cost of needing to drop the QSPI clock. Only
enable it on boards we've been able to validate.

Author: labbott

drv/auxflash-server/src/main.rs

@@ -19,7 +19,7 @@ use userlib::{hl, task_slot, RecvMessage, UnwrapLite};
 #[cfg(feature = "h753")]
 use stm32h7::stm32h753 as device;
 
-use drv_stm32h7_qspi::{Qspi, QspiError};
+use drv_stm32h7_qspi::{Qspi, QspiError, ReadSetting};
 use drv_stm32xx_sys_api as sys_api;
 
 task_slot!(SYS, sys);
@@ -71,7 +71,8 @@ fn main() -> ! {
     sys.leave_reset(sys_api::Peripheral::QuadSpi);
 
     let reg = unsafe { &*device::QUADSPI::ptr() };
-    let qspi = Qspi::new(reg, notifications::QSPI_IRQ_MASK);
+    let qspi =
+        Qspi::new(reg, notifications::QSPI_IRQ_MASK, ReadSetting::Single);
 
     let clock = 5; // 200MHz kernel / 5 = 40MHz clock
     const MEMORY_SIZE: usize = SLOT_COUNT as usize * SLOT_SIZE;

drv/gimlet-hf-server/src/bsp/gimlet_bcdef.rs

@@ -8,7 +8,9 @@ use drv_stm32xx_sys_api as sys_api;
 
 #[allow(dead_code)]
 pub(crate) fn init(qspi: &Qspi, sys: &sys_api::Sys) -> Config {
-    let clock = 6; // 200MHz kernel / 6 = 33.333MHz clock
+    // 33.33MHz was too fast to be able to use the full
+    // quad read commands, this seems to work
+    let clock = 7; // 200MHz kernel / 7 = 28.5714MHz clock
     qspi.configure(
         clock, 25, // 2**25 = 32MiB = 256Mib
     );

drv/gimlet-hf-server/src/main.rs

@@ -28,7 +28,7 @@ use userlib::{
 };
 
 use drv_hf_api::{HashData, HashState, SlotHash, SECTOR_SIZE_BYTES};
-use drv_stm32h7_qspi::{Qspi, QspiError};
+use drv_stm32h7_qspi::{Qspi, QspiError, ReadSetting};
 use drv_stm32xx_sys_api as sys_api;
 use idol_runtime::{
     ClientError, Leased, LenLimit, NotificationHandler, RequestError, R, W,
@@ -97,7 +97,7 @@ fn main() -> ! {
     sys.leave_reset(sys_api::Peripheral::QuadSpi);
 
     let reg = unsafe { &*device::QUADSPI::ptr() };
-    let qspi = Qspi::new(reg, notifications::QSPI_IRQ_MASK);
+    let qspi = Qspi::new(reg, notifications::QSPI_IRQ_MASK, ReadSetting::Quad);
 
     // Build a pin struct using a board-specific init function
     let cfg = bsp::init(&qspi, &sys);

drv/qspi-api/src/lib.rs

@@ -22,6 +22,7 @@ pub const PAGE_SIZE_BYTES: usize = 256;
 /// will need to change to something more flexible.
 pub const SECTOR_SIZE_BYTES: usize = 65_536;
 
+#[derive(Copy, Clone)]
 pub enum Command {
     ReadStatusReg = 0x05,
     WriteEnable = 0x06,
@@ -36,6 +37,12 @@ pub enum Command {
 
     BulkErase = 0xC7,
     SectorErase = 0xDC,
+    // 4-BYTE QUAD OUTPUT FAST READ
+    QuadRead = 0x6C,
+    // 4-BYTE DTR QUAD INPUT/OUTPUT FAST READ
+    // Does not work at the moment
+    QuadDdrRead = 0xEE,
+    DdrRead = 0x0E,
 }
 
 impl From<Command> for u8 {

drv/stm32h7-qspi/src/lib.rs

@@ -19,10 +19,19 @@ use zerocopy::IntoBytes;
 const FIFO_SIZE: usize = 32;
 const FIFO_THRESH: usize = 16;
 
+// In a perfect world we would use quad read everywhere because it is fast.
+// We've seen some inconsistency with the quad read command on some targets
+// so limit its use to targets where we've confirmed.
+pub enum ReadSetting {
+    Single,
+    Quad,
+}
+
 /// Wrapper for a reference to the register block.
 pub struct Qspi {
     reg: &'static device::quadspi::RegisterBlock,
     interrupt: u32,
+    read_command: Command,
 }
 
 pub enum QspiError {
@@ -35,8 +44,16 @@ impl Qspi {
     pub fn new(
         reg: &'static device::quadspi::RegisterBlock,
         interrupt: u32,
+        read: ReadSetting,
     ) -> Self {
-        Self { reg, interrupt }
+        Self {
+            reg,
+            interrupt,
+            read_command: match read {
+                ReadSetting::Single => Command::Read,
+                ReadSetting::Quad => Command::QuadRead,
+            },
+        }
     }
 
     /// Sets up the QSPI controller with some canned settings.
@@ -94,7 +111,7 @@ impl Qspi {
         address: u32,
         data: &mut [u8],
     ) -> Result<(), QspiError> {
-        self.read_impl(Command::Read, Some(address), data)
+        self.read_impl(self.read_command, Some(address), data)
     }
 
     /// Sets the Write Enable Latch on the flash chip, allowing a write/erase
@@ -311,22 +328,32 @@ impl Qspi {
         // hanging around from some previous transfer -- ensure this:
         self.reg.fcr.write(|w| w.ctcf().set_bit());
 
+        let (quad_setting, ddr_setting) = match command {
+            Command::QuadRead => (true, false),
+            Command::QuadDdrRead => (true, true),
+            Command::DdrRead => (false, true),
+            _ => (false, false),
+        };
+
         #[rustfmt::skip]
         #[allow(clippy::bool_to_int_with_if)]
         self.reg.ccr.write(|w| unsafe {
             w
+                // Set DDR mode if quad read
+                .ddrm().bit(ddr_setting)
+                .dhhc().bit(ddr_setting)
                 // Indirect read
                 .fmode().bits(0b01)
-                // Data on single line, or no data
-                .dmode().bits(if out.is_empty() { 0b00 } else { 0b01 })
-                // Dummy cycles = 0 for this
-                .dcyc().bits(0)
+                // Data on single line, 4 lines if quad or no line
+                .dmode().bits(if out.is_empty() { 0b00 } else if quad_setting { 0b11 } else { 0b01 } )
+                // Dummy cycles = 0 for single read, 8 for quad
+                .dcyc().bits(if quad_setting { 8 } else { 0 })
                 // No alternate bytes
                 .abmode().bits(0)
                 // 32-bit address if present.
                 .adsize().bits(if addr.is_some() { 0b11 } else { 0b00 })
-                // ...on one line for now, if present.
-                .admode().bits(if addr.is_some() { 0b01 } else { 0b00 })
+                // ...on one line for now (or 4 for the DDR command), if present.
+                .admode().bits(if addr.is_some() { if ddr_setting { 0b11} else { 0b01 } } else { 0b00 })
                 // Instruction on single line
                 .imode().bits(0b01)
                 // And, the op