Fix use of platform in no-alloc contexts + dependency issues

Author: IsaacWoods

Cargo.toml

@@ -4,7 +4,7 @@ resolver = "2"
 
 [package]
 name = "acpi"
-version = "6.0.0"
+version = "6.0.1"
 authors = ["Isaac Woods"]
 repository = "https://github.com/rust-osdev/acpi"
 description = "A pure-Rust library for interacting with ACPI"
@@ -17,10 +17,10 @@ bit_field = "0.10.2"
 bitflags = "2.5.0"
 log = "0.4.20"
 spinning_top = "0.3.0"
-pci_types = { version = "0.10.0", public = true, optional = true }
+pci_types = { version = "0.10.0", public = true }
 byteorder = { version = "1.5.0", default-features = false }
 
 [features]
 default = ["alloc", "aml"]
 alloc = []
-aml = ["alloc", "pci_types"]
+aml = ["alloc"]

src/platform/interrupt.rs

@@ -13,6 +13,8 @@ use alloc::{alloc::Global, vec::Vec};
 use bit_field::BitField;
 use core::{alloc::Allocator, pin::Pin};
 
+pub use crate::sdt::madt::{Polarity, TriggerMode};
+
 #[derive(Debug, Clone)]
 #[non_exhaustive]
 pub enum InterruptModel<A: Allocator = Global> {
@@ -280,31 +282,6 @@ pub enum NmiProcessor {
     ProcessorUid(u32),
 }
 
-/// Polarity indicates what signal mode the interrupt line needs to be in to be considered 'active'.
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum Polarity {
-    SameAsBus,
-    ActiveHigh,
-    ActiveLow,
-}
-
-/// Trigger mode of an interrupt, describing how the interrupt is triggered.
-///
-/// When an interrupt is `Edge` triggered, it is triggered exactly once, when the interrupt
-/// signal goes from its opposite polarity to its active polarity.
-///
-/// For `Level` triggered interrupts, a continuous signal is emitted so long as the interrupt
-/// is in its active polarity.
-///
-/// `SameAsBus`-triggered interrupts will utilize the same interrupt triggering as the system bus
-/// they communicate across.
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub enum TriggerMode {
-    SameAsBus,
-    Edge,
-    Level,
-}
-
 /// Describes a difference in the mapping of an ISA interrupt to how it's mapped in other interrupt
 /// models. For example, if a device is connected to ISA IRQ 0 and IOAPIC input 2, an override will
 /// appear mapping source 0 to GSI 2. Currently these will only be created for ISA interrupt

src/sdt/madt.rs

@@ -1,7 +1,6 @@
 use crate::{
     AcpiError,
     AcpiTable,
-    platform::interrupt::{Polarity, TriggerMode},
     sdt::{ExtendedField, SdtHeader, Signature},
 };
 use bit_field::BitField;
@@ -419,6 +418,31 @@ pub struct MultiprocessorWakeupMailbox {
     pub reserved_for_firmware: [u64; 256],
 }
 
+/// Polarity indicates what signal mode the interrupt line needs to be in to be considered 'active'.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum Polarity {
+    SameAsBus,
+    ActiveHigh,
+    ActiveLow,
+}
+
+/// Trigger mode of an interrupt, describing how the interrupt is triggered.
+///
+/// When an interrupt is `Edge` triggered, it is triggered exactly once, when the interrupt
+/// signal goes from its opposite polarity to its active polarity.
+///
+/// For `Level` triggered interrupts, a continuous signal is emitted so long as the interrupt
+/// is in its active polarity.
+///
+/// `SameAsBus`-triggered interrupts will utilize the same interrupt triggering as the system bus
+/// they communicate across.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum TriggerMode {
+    SameAsBus,
+    Edge,
+    Level,
+}
+
 pub fn parse_mps_inti_flags(flags: u16) -> Result<(Polarity, TriggerMode), AcpiError> {
     let polarity = match flags.get_bits(0..2) {
         0b00 => Polarity::SameAsBus,