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RISC-V: Add intrinsics testcases for SiFive Xsfvqmaccqoq/dod extensions.
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‎gcc/testsuite/gcc.target/riscv/rvv/rvv.exp‎

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@@ -37,6 +37,8 @@ dg-init
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set CFLAGS "$DEFAULT_CFLAGS -O3"
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dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
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"" $CFLAGS
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dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xsfvector/*.\[cS\]]] \
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"" $CFLAGS
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gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
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"" $CFLAGS
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dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \

‎gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c‎

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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_xsfvqmaccdod -mabi=lp64d -O3" } */
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/* { dg-final { check-function-bodies "**" "" } } */
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#include "riscv_vector.h"
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/*
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** test_sf_vqmacc_2x8x2_i32m1_vint32m1_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m1_t
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test_sf_vqmacc_2x8x2_i32m1_vint32m1_t (vint32m1_t vd, vint8m1_t vs1,
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vint8m1_t vs2, size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2_i32m1 (vd, vs1, vs2, vl);
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}
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/*
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** test_sf_vqmacc_2x8x2_i32m2_vint32m2_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m2_t
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test_sf_vqmacc_2x8x2_i32m2_vint32m2_t (vint32m2_t vd, vint8m1_t vs1,
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vint8m2_t vs2, size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2_i32m2 (vd, vs1, vs2, vl);
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}
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/*
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** test_sf_vqmacc_2x8x2_i32m4_vint32m4_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m4_t
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test_sf_vqmacc_2x8x2_i32m4_vint32m4_t (vint32m4_t vd, vint8m1_t vs1,
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vint8m4_t vs2, size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2_i32m4 (vd, vs1, vs2, vl);
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}
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/*
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** test_sf_vqmacc_2x8x2_i32m8_vint32m8_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m8_t
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test_sf_vqmacc_2x8x2_i32m8_vint32m8_t (vint32m8_t vd, vint8m1_t vs1,
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vint8m8_t vs2, size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2_i32m8 (vd, vs1, vs2, vl);
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}
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/*
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** test_sf_vqmacc_2x8x2_vint32m1_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m1_t
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test_sf_vqmacc_2x8x2_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2,
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size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2 (vd, vs1, vs2, vl);
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}
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/*
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** test_sf_vqmacc_2x8x2_vint32m2_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m2_t
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test_sf_vqmacc_2x8x2_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2,
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size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2 (vd, vs1, vs2, vl);
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}
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/*
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** test_sf_vqmacc_2x8x2_vint32m4_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m4_t
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test_sf_vqmacc_2x8x2_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2,
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size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2 (vd, vs1, vs2, vl);
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}
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/*
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** test_sf_vqmacc_2x8x2_vint32m8_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m8_t
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test_sf_vqmacc_2x8x2_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2,
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size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2 (vd, vs1, vs2, vl);
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}
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/*
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** test_sf_vqmacc_2x8x2_i32m1_tu_vint32m1_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m1_t
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test_sf_vqmacc_2x8x2_i32m1_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1,
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vint8m1_t vs2, size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2_i32m1_tu (vd, vs1, vs2, vl);
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}
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/*
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** test_sf_vqmacc_2x8x2_i32m2_tu_vint32m2_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m2_t
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test_sf_vqmacc_2x8x2_i32m2_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1,
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vint8m2_t vs2, size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2_i32m2_tu (vd, vs1, vs2, vl);
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}
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/*
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** test_sf_vqmacc_2x8x2_i32m4_tu_vint32m4_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m4_t
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test_sf_vqmacc_2x8x2_i32m4_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1,
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vint8m4_t vs2, size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2_i32m4_tu (vd, vs1, vs2, vl);
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}
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/*
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** test_sf_vqmacc_2x8x2_i32m8_tu_vint32m8_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m8_t
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test_sf_vqmacc_2x8x2_i32m8_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1,
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vint8m8_t vs2, size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2_i32m8_tu (vd, vs1, vs2, vl);
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}
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/*
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** test_sf_vqmacc_2x8x2_tu_vint32m1_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m1_t
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test_sf_vqmacc_2x8x2_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2,
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size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2_tu (vd, vs1, vs2, vl);
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}
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/*
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** test_sf_vqmacc_2x8x2_tu_vint32m2_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m2_t
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test_sf_vqmacc_2x8x2_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2,
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size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2_tu (vd, vs1, vs2, vl);
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}
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/*
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** test_sf_vqmacc_2x8x2_tu_vint32m4_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m4_t
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test_sf_vqmacc_2x8x2_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2,
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size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2_tu (vd, vs1, vs2, vl);
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}
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/*
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** test_sf_vqmacc_2x8x2_tu_vint32m8_t:
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** ...
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** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
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** ...
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*/
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vint32m8_t
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test_sf_vqmacc_2x8x2_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2,
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size_t vl)
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{
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return __riscv_sf_vqmacc_2x8x2_tu (vd, vs1, vs2, vl);
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}

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