Merge #452

452: update ci, clippy & release 0.10 r=therealprof a=burrbull



Co-authored-by: Andrey Zgarbul <[email protected]>

Author: bors[bot]

.github/workflows/ci.yml

@@ -24,17 +24,17 @@ jobs:
             experimental: true
 
     steps:
-      - uses: actions/checkout@v2
-      - uses: actions-rs/toolchain@v1
-        with:
-          profile: minimal
-          toolchain: ${{ matrix.rust }}
-          target: thumbv7m-none-eabi
-          override: true
+      - uses: actions/checkout@v3
+      - name: Use the latest ${{ matrix.rust }} rustc
+        run: rustup update ${{ matrix.rust }} && rustup default ${{ matrix.rust }}
+      - name: Add Cortex-M3 target
+        run: rustup target add thumbv7m-none-eabi
+
       - uses: actions-rs/cargo@v1
         with:
           command: check
           args: --features=${{ matrix.mcu }},rt --examples
+
       - uses: actions-rs/cargo@v1
         with:
           command: test

.github/workflows/clippy.yml

@@ -5,13 +5,12 @@ jobs:
   clippy_check:
     runs-on: ubuntu-latest
     steps:
-      - uses: actions/checkout@v1
-      - run: rustup component add clippy
-      - uses: actions-rs/toolchain@v1
-        with:
-          toolchain: stable
-          target: thumbv7m-none-eabi
-          override: true
+      - uses: actions/checkout@v3
+      - name: Use the latest stable rustc
+        run: rustup update stable && rustup default stable
+      - name: Add Cortex-M3 target
+        run: rustup target add thumbv7m-none-eabi
+
       - uses: actions-rs/clippy-check@v1
         with:
           token: ${{ secrets.GITHUB_TOKEN }}

.github/workflows/rustfmt.yml

@@ -7,13 +7,10 @@ jobs:
     name: Rustfmt
     runs-on: ubuntu-latest
     steps:
-      - uses: actions/checkout@v2
-      - uses: actions-rs/toolchain@v1
-        with:
-          profile: minimal
-          toolchain: stable
-          override: true
-      - run: rustup component add rustfmt
+      - uses: actions/checkout@v3
+      - name: Use the latest stable rustc
+        run: rustup update stable && rustup default stable
+
       - uses: actions-rs/cargo@v1
         with:
           command: fmt

CHANGELOG.md

@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.10.0] - 2022-12-12
+
 - `Timer`: adds `get_interrupt` to `Timer`
 - `gpio`: port and pin generics first, then mode,
   `PinMode` for modes instead of pins, `HL` trait, other cleanups
@@ -332,7 +334,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - First tagged version
 
-[Unreleased]: https://github.com/stm32-rs/stm32f1xx-hal/compare/v0.9.0...HEAD
+[Unreleased]: https://github.com/stm32-rs/stm32f1xx-hal/compare/v0.10.0...HEAD
+[v0.10.0]: https://github.com/stm32-rs/stm32f1xx-hal/compare/v0.9.0...v0.10.0
 [v0.9.0]: https://github.com/stm32-rs/stm32f1xx-hal/compare/v0.8.0...v0.9.0
 [v0.8.0]: https://github.com/stm32-rs/stm32f1xx-hal/compare/v0.7.0...v0.8.0
 [v0.7.0]: https://github.com/stm32-rs/stm32f1xx-hal/compare/v0.6.1...v0.7.0

Cargo.toml

@@ -11,10 +11,10 @@ name = "stm32f1xx-hal"
 repository = "https://github.com/stm32-rs/stm32f1xx-hal"
 documentation = "https://docs.rs/stm32f1xx-hal"
 readme = "README.md"
-version = "0.9.0"
+version = "0.10.0"
 
 [package.metadata.docs.rs]
-features = ["stm32f103", "rt"]
+features = ["stm32f103", "rtic", "high"]
 default-target = "x86_64-unknown-linux-gnu"
 
 [dependencies]

src/bb.rs

@@ -47,5 +47,5 @@ pub unsafe fn write<T>(register: *const T, bit: u8, set: bool) {
 
     let bit = bit as usize;
     let bb_addr = (PERI_BIT_BAND_BASE + (addr - PERI_ADDRESS_START) * 32) + 4 * bit;
-    ptr::write_volatile(bb_addr as *mut u32, if set { 1 } else { 0 });
+    ptr::write_volatile(bb_addr as *mut u32, u32::from(set));
 }

src/i2c.rs

@@ -243,7 +243,7 @@ where
     fn send_addr(&self, addr: u8, read: bool) {
         self.i2c
             .dr
-            .write(|w| w.dr().bits(addr << 1 | (if read { 1 } else { 0 })));
+            .write(|w| w.dr().bits(addr << 1 | (u8::from(read))));
     }
 
     /// Generate STOP condition

src/rcc.rs

@@ -266,12 +266,9 @@ impl CFGR {
                 .bits(if cfg.pllmul.is_some() {
                     // PLL
                     0b10
-                } else if cfg.hse.is_some() {
-                    // HSE
-                    0b1
                 } else {
-                    // HSI
-                    0b0
+                    // HSE or HSI
+                    u8::from(cfg.hse.is_some())
                 })
         });