Skip to content

Commit 26b7498

Browse files
committed
Avoid dual input+clobber registers
As far as I can tell, this has only been a problem with the C backend (see ziglang#25229), which is specifically excluded from this inline asm call. However, it's probably best to avoid it anyway and use output registers instead. In this case, because we're ignoring r3, which is the real "output" of the syscall, we can specify r0 as the sole `->` output instead, avoiding the need for a separate variable.
1 parent fa28560 commit 26b7498

File tree

2 files changed

+6
-6
lines changed

2 files changed

+6
-6
lines changed

lib/std/os/linux/powerpc.zig

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -200,11 +200,11 @@ pub fn restore_rt() callconv(.naked) noreturn {
200200
:
201201
: [number] "i" (@intFromEnum(SYS.rt_sigreturn)),
202202
: .{ .memory = true, .cr0 = true, .r0 = true, .r3 = true, .r4 = true, .r5 = true, .r6 = true, .r7 = true, .r8 = true, .r9 = true, .r10 = true, .r11 = true, .r12 = true, .ctr = true, .xer = true }),
203-
else => asm volatile (
203+
else => _ = asm volatile (
204204
\\ sc
205-
:
205+
: [r0] "={r0}" (-> usize), // r0 is clobbered
206206
: [number] "{r0}" (@intFromEnum(SYS.rt_sigreturn)),
207-
: .{ .memory = true, .cr0 = true, .r0 = true, .r3 = true, .r4 = true, .r5 = true, .r6 = true, .r7 = true, .r8 = true, .r9 = true, .r10 = true, .r11 = true, .r12 = true, .ctr = true, .xer = true }),
207+
: .{ .memory = true, .cr0 = true, .r3 = true, .r4 = true, .r5 = true, .r6 = true, .r7 = true, .r8 = true, .r9 = true, .r10 = true, .r11 = true, .r12 = true, .ctr = true, .xer = true }),
208208
}
209209
}
210210

lib/std/os/linux/powerpc64.zig

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -185,11 +185,11 @@ pub fn restore_rt() callconv(.naked) noreturn {
185185
:
186186
: [number] "i" (@intFromEnum(SYS.rt_sigreturn)),
187187
: .{ .memory = true, .cr0 = true, .r0 = true, .r3 = true, .r4 = true, .r5 = true, .r6 = true, .r7 = true, .r8 = true, .r9 = true, .r10 = true, .r11 = true, .r12 = true, .ctr = true, .xer = true }),
188-
else => asm volatile (
188+
else => _ = asm volatile (
189189
\\ sc
190-
:
190+
: [r0] "={r0}" (-> usize), // r0 is clobbered
191191
: [number] "{r0}" (@intFromEnum(SYS.rt_sigreturn)),
192-
: .{ .memory = true, .cr0 = true, .r0 = true, .r3 = true, .r4 = true, .r5 = true, .r6 = true, .r7 = true, .r8 = true, .r9 = true, .r10 = true, .r11 = true, .r12 = true, .ctr = true, .xer = true }),
192+
: .{ .memory = true, .cr0 = true, .r3 = true, .r4 = true, .r5 = true, .r6 = true, .r7 = true, .r8 = true, .r9 = true, .r10 = true, .r11 = true, .r12 = true, .ctr = true, .xer = true }),
193193
}
194194
}
195195

0 commit comments

Comments
 (0)