Simplified p2p mod based on the one by geohot

aikitoria · epictz06 · commit b3e12d6d63db · 2025-07-09T23:13:35.000+03:30
• Add install.sh wrapper for easier setup
• Refactor nv-pci.c for cleaner peer-to-peer init
• Update generated g_kern_bus_nvoc.c to handle new flags
• Tidy up kernel_bif and kern_bus_gp100 for consistency
• Adjust nv_gpu_ops and gmmu_fmt for P2P mapping support
diff --git a/install.sh b/install.sh
@@ -0,0 +1,7 @@
+#!/bin/bash
+sudo rmmod nvidia_drm nvidia_modeset nvidia_uvm nvidia
+set -e
+make modules -j$(nproc)
+sudo make modules_install -j$(nproc)
+sudo depmod
+nvidia-smi
diff --git a/kernel-open/nvidia/nv-pci.c b/kernel-open/nvidia/nv-pci.c
@@ -187,11 +187,11 @@ static int nv_resize_pcie_bars(struct pci_dev *pci_dev) {
     struct pci_host_bridge *host;
 #endif
 
-    if (NVreg_EnableResizableBar == 0)
+    /*if (NVreg_EnableResizableBar == 0)
     {
         nv_printf(NV_DBG_INFO, "NVRM: resizable BAR disabled by regkey, skipping\n");
         return 0;
-    }
+    }*/
 
     // Check if BAR1 has PCIe rebar capabilities
     sizes = pci_rebar_get_possible_sizes(pci_dev, NV_GPU_BAR1);
diff --git a/src/nvidia/generated/g_kern_bus_nvoc.c b/src/nvidia/generated/g_kern_bus_nvoc.c
@@ -752,7 +752,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner *
     // default
     else
     {
-        pThis->__kbusGetBar1P2PDmaInfo__ = &kbusGetBar1P2PDmaInfo_395e98;
+        pThis->__kbusGetBar1P2PDmaInfo__ = &kbusGetBar1P2PDmaInfo_GH100;
     }
 
     // kbusCreateP2PMappingForBar1P2P -- halified (2 hals) body
@@ -764,7 +764,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner *
     // default
     else
     {
-        pThis->__kbusCreateP2PMappingForBar1P2P__ = &kbusCreateP2PMappingForBar1P2P_395e98;
+        pThis->__kbusCreateP2PMappingForBar1P2P__ = &kbusCreateP2PMappingForBar1P2P_GH100;
     }
 
     // kbusRemoveP2PMappingForBar1P2P -- halified (2 hals) body
@@ -776,7 +776,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner *
     // default
     else
     {
-        pThis->__kbusRemoveP2PMappingForBar1P2P__ = &kbusRemoveP2PMappingForBar1P2P_395e98;
+        pThis->__kbusRemoveP2PMappingForBar1P2P__ = &kbusRemoveP2PMappingForBar1P2P_GH100;
     }
 
     // kbusHasPcieBar1P2PMapping -- halified (2 hals) body
@@ -788,7 +788,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner *
     // default
     else
     {
-        pThis->__kbusHasPcieBar1P2PMapping__ = &kbusHasPcieBar1P2PMapping_d69453;
+        pThis->__kbusHasPcieBar1P2PMapping__ = &kbusHasPcieBar1P2PMapping_GH100;
     }
 
     // kbusIsPcieBar1P2PMappingSupported -- halified (2 hals) body
@@ -800,7 +800,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner *
     // default
     else
     {
-        pThis->__kbusIsPcieBar1P2PMappingSupported__ = &kbusIsPcieBar1P2PMappingSupported_d69453;
+        pThis->__kbusIsPcieBar1P2PMappingSupported__ = &kbusIsPcieBar1P2PMappingSupported_GH100;
     }
 
     // kbusCheckFlaSupportedAndInit -- halified (2 hals) body
diff --git a/src/nvidia/src/kernel/gpu/bif/kernel_bif.c b/src/nvidia/src/kernel/gpu/bif/kernel_bif.c
@@ -772,7 +772,7 @@ _kbifInitRegistryOverrides
     NvU32 data32;
 
     // P2P Override
-    pKernelBif->p2pOverride = BIF_P2P_NOT_OVERRIDEN;
+    pKernelBif->p2pOverride = 0x11;
     if (osReadRegistryDword(pGpu, NV_REG_STR_CL_FORCE_P2P, &data32) == NV_OK)
     {
         pKernelBif->p2pOverride = data32;
@@ -781,7 +781,7 @@ _kbifInitRegistryOverrides
     }
 
     // P2P force type override
-    pKernelBif->forceP2PType = NV_REG_STR_RM_FORCE_P2P_TYPE_DEFAULT;
+    pKernelBif->forceP2PType = NV_REG_STR_RM_FORCE_P2P_TYPE_BAR1P2P;
     if (osReadRegistryDword(pGpu, NV_REG_STR_RM_FORCE_P2P_TYPE, &data32) == NV_OK &&
         (data32 <= NV_REG_STR_RM_FORCE_P2P_TYPE_MAX))
     {
diff --git a/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c b/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c
@@ -65,6 +65,11 @@ kbusCreateP2PMapping_GP100
         return kbusCreateP2PMappingForNvlink_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes);
     }
 
+    if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _PCIE_BAR1, attributes))
+    {
+        return kbusCreateP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes);
+    }
+
     if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _PCIE, attributes))
     {
         return kbusCreateP2PMappingForMailbox_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes);
@@ -632,6 +637,11 @@ kbusRemoveP2PMapping_GP100
         return kbusRemoveP2PMappingForNvlink_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes);
     }
 
+    if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _PCIE_BAR1, attributes))
+    {
+        return kbusRemoveP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes);
+    }
+
     if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _PCIE, attributes))
     {
         return kbusRemoveP2PMappingForMailbox_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes);
diff --git a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c
@@ -3669,7 +3669,8 @@ nvGpuOpsBuildExternalAllocPtes
     NvBool      isIndirectPeerSupported,
     NvBool      isPeerSupported,
     NvU32       peerId,
-    gpuExternalMappingInfo *pGpuExternalMappingInfo
+    gpuExternalMappingInfo *pGpuExternalMappingInfo,
+    RmPhysAddr bar1BusAddr
 )
 {
     NV_STATUS               status              = NV_OK;
@@ -3864,7 +3865,11 @@ nvGpuOpsBuildExternalAllocPtes
         if (nvFieldIsValid32(&pPteFmt->fldAtomicDisable.desc))
             nvFieldSetBool(&pPteFmt->fldAtomicDisable, !atomic, pte.v8);
 
+        if (aperture == GMMU_APERTURE_PEER) {
+            gmmuFieldSetAperture(&pPteFmt->fldAperture, GMMU_APERTURE_SYS_NONCOH, pte.v8);
+        } else {
         gmmuFieldSetAperture(&pPteFmt->fldAperture, aperture, pte.v8);
+        }
 
         if (!isCompressedKind)
         {
@@ -3875,7 +3880,11 @@ nvGpuOpsBuildExternalAllocPtes
         }
     }
 
-    if (aperture == GMMU_APERTURE_PEER)
+    if (aperture == GMMU_APERTURE_PEER) {
+        fabricBaseAddress = bar1BusAddr;
+    }
+
+    /*if (aperture == GMMU_APERTURE_PEER)
     {
         FlaMemory* pFlaMemory = dynamicCast(pMemory, FlaMemory);
         nvFieldSet32(&pPteFmt->fldPeerIndex, peerId, pte.v8);
@@ -3914,7 +3923,7 @@ nvGpuOpsBuildExternalAllocPtes
                 }
             }
         }
-    }
+    }*/
 
     //
     // Both memdescGetPhysAddr() and kgmmuEncodePhysAddr() have pretty high overhead.
@@ -4072,7 +4081,8 @@ nvGpuOpsBuildExternalAllocPhysAddrs
     NvBool      isIndirectPeerSupported,
     NvBool      isPeerSupported,
     NvU32       peerId,
-    UvmGpuExternalPhysAddrInfo *pGpuExternalPhysAddrInfo
+    UvmGpuExternalPhysAddrInfo *pGpuExternalPhysAddrInfo,
+    RmPhysAddr bar1BusAddr
 )
 {
     NV_STATUS               status              = NV_OK;
@@ -4145,7 +4155,11 @@ nvGpuOpsBuildExternalAllocPhysAddrs
         return NV_ERR_BUFFER_TOO_SMALL;
 
 
-    if (aperture == GMMU_APERTURE_PEER)
+    if (aperture == GMMU_APERTURE_PEER) {
+        fabricBaseAddress = bar1BusAddr;
+    }
+
+    /*if (aperture == GMMU_APERTURE_PEER)
     {
         FlaMemory* pFlaMemory = dynamicCast(pMemory, FlaMemory);
 
@@ -4183,7 +4197,7 @@ nvGpuOpsBuildExternalAllocPhysAddrs
                 }
             }
         }
-    }
+    }*/
 
     //
     // Both memdescGetPhysAddr() and kgmmuEncodePhysAddr() have pretty high overhead.
@@ -4235,6 +4249,7 @@ NV_STATUS nvGpuOpsGetExternalAllocPtesOrPhysAddrs(struct gpuAddressSpace *vaSpac
     Memory *pMemory = NULL;
     PMEMORY_DESCRIPTOR pMemDesc = NULL;
     OBJGPU *pMappingGpu = NULL;
+    RmPhysAddr bar1BusAddr = 0;
     NvU32 peerId = 0;
     NvBool isSliSupported = NV_FALSE;
     NvBool isPeerSupported = NV_FALSE;
@@ -4386,6 +4401,8 @@ NV_STATUS nvGpuOpsGetExternalAllocPtesOrPhysAddrs(struct gpuAddressSpace *vaSpac
                                                        &peerId);
             if (status != NV_OK)
                 goto freeGpaMemdesc;
+
+            bar1BusAddr = gpumgrGetGpuPhysFbAddr(pAdjustedMemDesc->pGpu);
         }
 
         //
@@ -4465,14 +4482,14 @@ NV_STATUS nvGpuOpsGetExternalAllocPtesOrPhysAddrs(struct gpuAddressSpace *vaSpac
     {
         status = nvGpuOpsBuildExternalAllocPtes(pVAS, pMappingGpu, pAdjustedMemDesc, pMemory, offset, size,
                                                 isIndirectPeerSupported, isPeerSupported, peerId,
-                                                pGpuExternalMappingInfo);
+                                                pGpuExternalMappingInfo, bar1BusAddr);
     }
 
     if (pGpuExternalPhysAddrInfo != NULL)
     {
         status = nvGpuOpsBuildExternalAllocPhysAddrs(pVAS, pMappingGpu, pAdjustedMemDesc, pMemory, offset, size,
                                                      isIndirectPeerSupported, isPeerSupported, peerId,
-                                                     pGpuExternalPhysAddrInfo);
+                                                     pGpuExternalPhysAddrInfo, bar1BusAddr);
     }
 
 freeGpaMemdesc:
@@ -10309,7 +10326,7 @@ NV_STATUS nvGpuOpsGetChannelResourcePtes(struct gpuAddressSpace *vaSpace,
 
     status = nvGpuOpsBuildExternalAllocPtes(pVAS, pMappingGpu, pMemDesc, NULL,
                                             offset, size, NV_FALSE, NV_FALSE,
-                                            0, pGpuExternalMappingInfo);
+                                            0, pGpuExternalMappingInfo, 0);
 
     _nvGpuOpsLocksRelease(&acquiredLocks);
     threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
diff --git a/src/nvidia/src/libraries/mmu/gmmu_fmt.c b/src/nvidia/src/libraries/mmu/gmmu_fmt.c
@@ -124,9 +124,8 @@ gmmuFmtPtePhysAddrFld
     {
         case GMMU_APERTURE_SYS_COH:
         case GMMU_APERTURE_SYS_NONCOH:
-            return &pPte->fldAddrSysmem;
         case GMMU_APERTURE_PEER:
-            return &pPte->fldAddrPeer;
+            return &pPte->fldAddrSysmem;
         case GMMU_APERTURE_VIDEO:
             return &pPte->fldAddrVidmem;
         default:

Original file line number	Diff line number	Diff line change
`@@ -752,7 +752,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus pThis, RmHalspecOwner `
`752`	`752`	`// default`
`753`	`753`	`else`
`754`	`754`	`{`
`755`		`- pThis->__kbusGetBar1P2PDmaInfo__ = &kbusGetBar1P2PDmaInfo_395e98;`
	`755`	`+ pThis->__kbusGetBar1P2PDmaInfo__ = &kbusGetBar1P2PDmaInfo_GH100;`
`756`	`756`	`}`
`757`	`757`
`758`	`758`	`// kbusCreateP2PMappingForBar1P2P -- halified (2 hals) body`
`@@ -764,7 +764,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus pThis, RmHalspecOwner `
`764`	`764`	`// default`
`765`	`765`	`else`
`766`	`766`	`{`
`767`		`- pThis->__kbusCreateP2PMappingForBar1P2P__ = &kbusCreateP2PMappingForBar1P2P_395e98;`
	`767`	`+ pThis->__kbusCreateP2PMappingForBar1P2P__ = &kbusCreateP2PMappingForBar1P2P_GH100;`
`768`	`768`	`}`
`769`	`769`
`770`	`770`	`// kbusRemoveP2PMappingForBar1P2P -- halified (2 hals) body`
`@@ -776,7 +776,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus pThis, RmHalspecOwner `
`776`	`776`	`// default`
`777`	`777`	`else`
`778`	`778`	`{`
`779`		`- pThis->__kbusRemoveP2PMappingForBar1P2P__ = &kbusRemoveP2PMappingForBar1P2P_395e98;`
	`779`	`+ pThis->__kbusRemoveP2PMappingForBar1P2P__ = &kbusRemoveP2PMappingForBar1P2P_GH100;`
`780`	`780`	`}`
`781`	`781`
`782`	`782`	`// kbusHasPcieBar1P2PMapping -- halified (2 hals) body`
`@@ -788,7 +788,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus pThis, RmHalspecOwner `
`788`	`788`	`// default`
`789`	`789`	`else`
`790`	`790`	`{`
`791`		`- pThis->__kbusHasPcieBar1P2PMapping__ = &kbusHasPcieBar1P2PMapping_d69453;`
	`791`	`+ pThis->__kbusHasPcieBar1P2PMapping__ = &kbusHasPcieBar1P2PMapping_GH100;`
`792`	`792`	`}`
`793`	`793`
`794`	`794`	`// kbusIsPcieBar1P2PMappingSupported -- halified (2 hals) body`
`@@ -800,7 +800,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus pThis, RmHalspecOwner `
`800`	`800`	`// default`
`801`	`801`	`else`
`802`	`802`	`{`
`803`		`- pThis->__kbusIsPcieBar1P2PMappingSupported__ = &kbusIsPcieBar1P2PMappingSupported_d69453;`
	`803`	`+ pThis->__kbusIsPcieBar1P2PMappingSupported__ = &kbusIsPcieBar1P2PMappingSupported_GH100;`
`804`	`804`	`}`
`805`	`805`
`806`	`806`	`// kbusCheckFlaSupportedAndInit -- halified (2 hals) body`
Original file line number	Diff line number	Diff line change
`@@ -772,7 +772,7 @@ _kbifInitRegistryOverrides`
`772`	`772`	`NvU32 data32;`
`773`	`773`
`774`	`774`	`// P2P Override`
`775`		`- pKernelBif->p2pOverride = BIF_P2P_NOT_OVERRIDEN;`
	`775`	`+ pKernelBif->p2pOverride = 0x11;`
`776`	`776`	`if (osReadRegistryDword(pGpu, NV_REG_STR_CL_FORCE_P2P, &data32) == NV_OK)`
`777`	`777`	`{`
`778`	`778`	`pKernelBif->p2pOverride = data32;`
`@@ -781,7 +781,7 @@ _kbifInitRegistryOverrides`
`781`	`781`	`}`
`782`	`782`
`783`	`783`	`// P2P force type override`
`784`		`- pKernelBif->forceP2PType = NV_REG_STR_RM_FORCE_P2P_TYPE_DEFAULT;`
	`784`	`+ pKernelBif->forceP2PType = NV_REG_STR_RM_FORCE_P2P_TYPE_BAR1P2P;`
`785`	`785`	`if (osReadRegistryDword(pGpu, NV_REG_STR_RM_FORCE_P2P_TYPE, &data32) == NV_OK &&`
`786`	`786`	`(data32 <= NV_REG_STR_RM_FORCE_P2P_TYPE_MAX))`
`787`	`787`	`{`
Original file line number	Diff line number	Diff line change
`@@ -65,6 +65,11 @@ kbusCreateP2PMapping_GP100`
`65`	`65`	`return kbusCreateP2PMappingForNvlink_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes);`
`66`	`66`	`}`
`67`	`67`
	`68`	`+ if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _PCIE_BAR1, attributes))`
	`69`	`+ {`
	`70`	`+ return kbusCreateP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes);`
	`71`	`+ }`
	`72`	`+`
`68`	`73`	`if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _PCIE, attributes))`
`69`	`74`	`{`
`70`	`75`	`return kbusCreateP2PMappingForMailbox_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes);`
`@@ -632,6 +637,11 @@ kbusRemoveP2PMapping_GP100`
`632`	`637`	`return kbusRemoveP2PMappingForNvlink_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes);`
`633`	`638`	`}`
`634`	`639`
	`640`	`+ if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _PCIE_BAR1, attributes))`
	`641`	`+ {`
	`642`	`+ return kbusRemoveP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes);`
	`643`	`+ }`
	`644`	`+`
`635`	`645`	`if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _PCIE, attributes))`
`636`	`646`	`{`
`637`	`647`	`return kbusRemoveP2PMappingForMailbox_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes);`
Original file line number	Diff line number	Diff line change
`@@ -3669,7 +3669,8 @@ nvGpuOpsBuildExternalAllocPtes`
`3669`	`3669`	`NvBool isIndirectPeerSupported,`
`3670`	`3670`	`NvBool isPeerSupported,`
`3671`	`3671`	`NvU32 peerId,`
`3672`		`- gpuExternalMappingInfo *pGpuExternalMappingInfo`
	`3672`	`+ gpuExternalMappingInfo *pGpuExternalMappingInfo,`
	`3673`	`+ RmPhysAddr bar1BusAddr`
`3673`	`3674`	`)`
`3674`	`3675`	`{`
`3675`	`3676`	`NV_STATUS status = NV_OK;`
`@@ -3864,7 +3865,11 @@ nvGpuOpsBuildExternalAllocPtes`
`3864`	`3865`	`if (nvFieldIsValid32(&pPteFmt->fldAtomicDisable.desc))`
`3865`	`3866`	`nvFieldSetBool(&pPteFmt->fldAtomicDisable, !atomic, pte.v8);`
`3866`	`3867`
	`3868`	`+ if (aperture == GMMU_APERTURE_PEER) {`
	`3869`	`+ gmmuFieldSetAperture(&pPteFmt->fldAperture, GMMU_APERTURE_SYS_NONCOH, pte.v8);`
	`3870`	`+ } else {`
`3867`	`3871`	`gmmuFieldSetAperture(&pPteFmt->fldAperture, aperture, pte.v8);`
	`3872`	`+ }`
`3868`	`3873`
`3869`	`3874`	`if (!isCompressedKind)`
`3870`	`3875`	`{`
`@@ -3875,7 +3880,11 @@ nvGpuOpsBuildExternalAllocPtes`
`3875`	`3880`	`}`
`3876`	`3881`	`}`
`3877`	`3882`
`3878`		`- if (aperture == GMMU_APERTURE_PEER)`
	`3883`	`+ if (aperture == GMMU_APERTURE_PEER) {`
	`3884`	`+ fabricBaseAddress = bar1BusAddr;`
	`3885`	`+ }`
	`3886`	`+`
	`3887`	`+ /*if (aperture == GMMU_APERTURE_PEER)`
`3879`	`3888`	`{`
`3880`	`3889`	`FlaMemory* pFlaMemory = dynamicCast(pMemory, FlaMemory);`
`3881`	`3890`	`nvFieldSet32(&pPteFmt->fldPeerIndex, peerId, pte.v8);`
`@@ -3914,7 +3923,7 @@ nvGpuOpsBuildExternalAllocPtes`
`3914`	`3923`	`}`
`3915`	`3924`	`}`
`3916`	`3925`	`}`
`3917`		`- }`
	`3926`	`+ }*/`
`3918`	`3927`
`3919`	`3928`	`//`
`3920`	`3929`	`// Both memdescGetPhysAddr() and kgmmuEncodePhysAddr() have pretty high overhead.`
`@@ -4072,7 +4081,8 @@ nvGpuOpsBuildExternalAllocPhysAddrs`
`4072`	`4081`	`NvBool isIndirectPeerSupported,`
`4073`	`4082`	`NvBool isPeerSupported,`
`4074`	`4083`	`NvU32 peerId,`
`4075`		`- UvmGpuExternalPhysAddrInfo *pGpuExternalPhysAddrInfo`
	`4084`	`+ UvmGpuExternalPhysAddrInfo *pGpuExternalPhysAddrInfo,`
	`4085`	`+ RmPhysAddr bar1BusAddr`
`4076`	`4086`	`)`
`4077`	`4087`	`{`
`4078`	`4088`	`NV_STATUS status = NV_OK;`
`@@ -4145,7 +4155,11 @@ nvGpuOpsBuildExternalAllocPhysAddrs`
`4145`	`4155`	`return NV_ERR_BUFFER_TOO_SMALL;`
`4146`	`4156`
`4147`	`4157`
`4148`		`- if (aperture == GMMU_APERTURE_PEER)`
	`4158`	`+ if (aperture == GMMU_APERTURE_PEER) {`
	`4159`	`+ fabricBaseAddress = bar1BusAddr;`
	`4160`	`+ }`
	`4161`	`+`
	`4162`	`+ /*if (aperture == GMMU_APERTURE_PEER)`
`4149`	`4163`	`{`
`4150`	`4164`	`FlaMemory* pFlaMemory = dynamicCast(pMemory, FlaMemory);`
`4151`	`4165`
`@@ -4183,7 +4197,7 @@ nvGpuOpsBuildExternalAllocPhysAddrs`
`4183`	`4197`	`}`
`4184`	`4198`	`}`
`4185`	`4199`	`}`
`4186`		`- }`
	`4200`	`+ }*/`
`4187`	`4201`
`4188`	`4202`	`//`
`4189`	`4203`	`// Both memdescGetPhysAddr() and kgmmuEncodePhysAddr() have pretty high overhead.`
`@@ -4235,6 +4249,7 @@ NV_STATUS nvGpuOpsGetExternalAllocPtesOrPhysAddrs(struct gpuAddressSpace *vaSpac`
`4235`	`4249`	`Memory *pMemory = NULL;`
`4236`	`4250`	`PMEMORY_DESCRIPTOR pMemDesc = NULL;`
`4237`	`4251`	`OBJGPU *pMappingGpu = NULL;`
	`4252`	`+ RmPhysAddr bar1BusAddr = 0;`
`4238`	`4253`	`NvU32 peerId = 0;`
`4239`	`4254`	`NvBool isSliSupported = NV_FALSE;`
`4240`	`4255`	`NvBool isPeerSupported = NV_FALSE;`
`@@ -4386,6 +4401,8 @@ NV_STATUS nvGpuOpsGetExternalAllocPtesOrPhysAddrs(struct gpuAddressSpace *vaSpac`
`4386`	`4401`	`&peerId);`
`4387`	`4402`	`if (status != NV_OK)`
`4388`	`4403`	`goto freeGpaMemdesc;`
	`4404`	`+`
	`4405`	`+ bar1BusAddr = gpumgrGetGpuPhysFbAddr(pAdjustedMemDesc->pGpu);`
`4389`	`4406`	`}`
`4390`	`4407`
`4391`	`4408`	`//`
`@@ -4465,14 +4482,14 @@ NV_STATUS nvGpuOpsGetExternalAllocPtesOrPhysAddrs(struct gpuAddressSpace *vaSpac`
`4465`	`4482`	`{`
`4466`	`4483`	`status = nvGpuOpsBuildExternalAllocPtes(pVAS, pMappingGpu, pAdjustedMemDesc, pMemory, offset, size,`
`4467`	`4484`	`isIndirectPeerSupported, isPeerSupported, peerId,`
`4468`		`- pGpuExternalMappingInfo);`
	`4485`	`+ pGpuExternalMappingInfo, bar1BusAddr);`
`4469`	`4486`	`}`
`4470`	`4487`
`4471`	`4488`	`if (pGpuExternalPhysAddrInfo != NULL)`
`4472`	`4489`	`{`
`4473`	`4490`	`status = nvGpuOpsBuildExternalAllocPhysAddrs(pVAS, pMappingGpu, pAdjustedMemDesc, pMemory, offset, size,`
`4474`	`4491`	`isIndirectPeerSupported, isPeerSupported, peerId,`
`4475`		`- pGpuExternalPhysAddrInfo);`
	`4492`	`+ pGpuExternalPhysAddrInfo, bar1BusAddr);`
`4476`	`4493`	`}`
`4477`	`4494`
`4478`	`4495`	`freeGpaMemdesc:`
`@@ -10309,7 +10326,7 @@ NV_STATUS nvGpuOpsGetChannelResourcePtes(struct gpuAddressSpace *vaSpace,`
`10309`	`10326`
`10310`	`10327`	`status = nvGpuOpsBuildExternalAllocPtes(pVAS, pMappingGpu, pMemDesc, NULL,`
`10311`	`10328`	`offset, size, NV_FALSE, NV_FALSE,`
`10312`		`- 0, pGpuExternalMappingInfo);`
	`10329`	`+ 0, pGpuExternalMappingInfo, 0);`
`10313`	`10330`
`10314`	`10331`	`_nvGpuOpsLocksRelease(&acquiredLocks);`
`10315`	`10332`	`threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);`