tt syntax fix?

Author: trsigg

_reading-groups/sp22/theory-thursdays.md

@@ -12,17 +12,17 @@ weeks:
     topic: >-
         Siqi Liu: Finding planar drawings for planar graphs
 
-        **Abstract:** In this short talk I will introduce the notion of graph Laplacian and show an algorithm that uses graph Laplacians to find planar drawings for planar graphs.
+        *   **Abstract:** In this short talk I will introduce the notion of graph Laplacian and show an algorithm that uses graph Laplacians to find planar drawings for planar graphs.
     resources: >-
         This talk is based on these [notes](http://cs-www.cs.yale.edu/homes/spielman/PAPERS/bull1557.pdf) by Dan Spielman
   
   - date: 4/6
     topic: >-
         Nate Young: VLSI lower bounds
 
-        **Abstract:** With the end of single-processor performance scaling and enormous popularity of very-high-compute applications like those in deep learning, there is more interest than ever in parallel computation and application-specific parallel hardware. Although parallel models like PRAMs are sometimes studied by theoreticians, these theoretical models fail to capture not only important constant factors but even some very important asymptotic costs incurred by real parallel computation. In this talk, I will give an introduction to a line of work that attempts to close this gap using theoretical models of integrated-circuit chips, and I will present a few asymptotic lower bounds on computation time and chip area using this much more realistic model.
+        *   **Abstract:** With the end of single-processor performance scaling and enormous popularity of very-high-compute applications like those in deep learning, there is more interest than ever in parallel computation and application-specific parallel hardware. Although parallel models like PRAMs are sometimes studied by theoreticians, these theoretical models fail to capture not only important constant factors but even some very important asymptotic costs incurred by real parallel computation. In this talk, I will give an introduction to a line of work that attempts to close this gap using theoretical models of integrated-circuit chips, and I will present a few asymptotic lower bounds on computation time and chip area using this much more realistic model.
     recources: >-
-        [Recording](https://drive.google.com/file/d/1b51TG6yi205mdVFkJzYqN6A9-mSQKHhs/view?usp=sharing)
+        *   [Recording](https://drive.google.com/file/d/1b51TG6yi205mdVFkJzYqN6A9-mSQKHhs/view?usp=sharing)
   
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