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loglav03loglav03
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Updating subtractor.cc, adder chain seems properly connected now
1 parent a216d50 commit 26213f9

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3 files changed

+186
-6
lines changed

3 files changed

+186
-6
lines changed

‎parmys/parmys-plugin/core/subtractor.cc‎

Lines changed: 169 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -572,12 +572,15 @@ void split_adder_for_sub(nnode_t *nodeo, int a, int b, int sizea, int sizeb, int
572572
//}
573573
// int W = nodeo->num_output_pins - 1;
574574
// int sums_mapped = 0;
575+
576+
575577
if (count > 1 || configuration.adder_cin_global) {
576578
// remap the output pins of each adder to nodeo
577-
for (int i = offset; i < count - 1; i++) {
579+
for (int i = offset; i < count; i++) {
578580
for (int j = 0; j < node[i]->num_output_pins - 1; j++) {
579-
if ((i * sizea + j - offset) < nodeo->num_output_pins-1){
581+
if ((i * sizea + j - offset) < nodeo->num_output_pins){
580582
remap_pin_to_new_node(nodeo->output_pins[i * sizea + j - offset], node[i], j + 1);
583+
nodeo->output_pins[i * sizea + j - offset] = NULL;
581584
}
582585
else {
583586
node[i]->output_pins[j + 1] = allocate_npin();
@@ -586,26 +589,186 @@ void split_adder_for_sub(nnode_t *nodeo, int a, int b, int sizea, int sizeb, int
586589
}
587590
}
588591
}
589-
remap_pin_to_new_node(nodeo->output_pins[nodeo->num_output_pins - 1], node[count - 1], 0);
592+
//remap_pin_to_new_node(nodeo->output_pins[nodeo->num_output_pins - 1], node[count - 1], 1);
590593
}
591-
//node[count - 1]->output_pins[1] = allocate_npin();
594+
node[count - 1]->output_pins[0] = allocate_npin();
595+
596+
597+
// const int W = nodeo->num_output_pins - 1; // number of sum bits
598+
// // 1) Map sums from all real slices EXCEPT the last slice (tail)
599+
// int sums = 0;
600+
// for (int i = offset; i < count - 1 && sums < W; ++i) {
601+
// const int sum_pins = node[i]->num_output_pins - 1; // skip pin0=cout
602+
// for (int j = 0; j < sum_pins && sums < W; ++j) {
603+
// int out_idx = /* pack densely or keep your spacing */ sums;
604+
// remap_pin_to_new_node(nodeo->output_pins[out_idx], node[i], /*from pin*/ j + 1);
605+
// nodeo->output_pins[out_idx] = NULL;
606+
607+
// // Optional: if remap nulls source slot, pad it to keep iteration safe later
608+
// if (node[i]->output_pins[j + 1] == nullptr) {
609+
// node[i]->output_pins[j + 1] = allocate_npin();
610+
// node[i]->output_pins[j + 1]->name =
611+
// append_string("", "%s~dummy_sum~%d~%d", node[i]->name, i, j + 1);
612+
// }
613+
// ++sums;
614+
// }
615+
// }
616+
// if (count > 0) {
617+
// remap_pin_to_new_node(nodeo->output_pins[W], node[count - 1], 1);
618+
// nodeo->output_pins[W] = NULL;
619+
// }
620+
// node[count - 1]->output_pins[0] = allocate_npin();
592621
//printf("Net of tail node: %s\n", node[5]->output_pins[1]->net);
593622
//std::cout << "TESTING " << node[5]->output_pins[1]->net->fanout_pins << "\n";
594623
//std::cout << "TESTING " << node[3]->output_pins[1]->net->fanout_pins << "\n";
595624
//remap_pin_to_new_node(nodeo->output_pins[nodeo->num_output_pins - 1], node[count - 1], 0);
596625
// Pad outputs with a unique and descriptive name to avoid collisions.
597-
//node[count - 1]->output_pins[0]->name = append_string("", "%s~dummy_output~%d~%d", node[(count - 1)]->name, (count - 1), 0);
626+
node[count - 1]->output_pins[0]->name = append_string("", "%s~dummy_output~%d~%d", node[(count - 1)]->name, (count - 1), 0);
598627
// connect_nodes(node[count - 1], (node[(count - 1)]->num_output_pins - 1), netlist->gnd_node, 0);
599628
// }
600629

630+
// for (int k = 0; k < nodeo->num_output_pins; ++k) {
631+
// oassert(nodeo->output_pins[k] == NULL);
632+
// }
633+
634+
// for (int i = 1; i < count; ++i) {
635+
// for (int p = 0; p < node[i]->num_output_pins; ++p) {
636+
// if(i == 5 && p ==0) continue;
637+
// oassert(node[i]->output_pins[p] != NULL);
638+
// oassert(node[i]->output_pins[p]->net != NULL);
639+
// oassert(node[i]->output_pins[p]->type == OUTPUT);
640+
// oassert(node[i]->output_pins[p]->node == node[i]);
641+
// oassert(node[i]->output_pins[p]->pin_node_idx == p);
642+
// }
643+
// }
644+
645+
// for (int i = offset; i < count-1; ++i)
646+
// oassert(node[i]->output_pins[1]->net->num_driver_pins == 1);
647+
// oassert(node[count-1]->output_pins[1]->net->num_driver_pins == 1); // MSB via sumout
648+
649+
// static const char* pin_role(const nnode_t* n, int pidx) {
650+
// // adder: pin 0 = cout, 1 = sumout. For other nodes, return an empty tag.
651+
// if (n && n->name && strstr(n->name, "adder")) {
652+
// return pidx == 0 ? "cout" : (pidx == 1 ? "sum" : "?");
653+
// }
654+
// return "";
655+
// }
656+
657+
// int po_count = netlist->num_top_output_nodes;
658+
659+
// for(int k = 0; k < po_count; k++) { //move through each primary output node
660+
// nnode_t* po = netlist->top_output_nodes[k]; //po is PO[k]
661+
// oassert(po);
662+
// oassert(po->num_input_pins >= 1);
663+
// npin_t* in = po->input_pins[0]; //in is input pin to po
664+
// char tag[64]; snprintf(tag, sizeof(tag), "PO[%d] %s.in0", k, po->name ? po->name : "out");
665+
666+
// oassert(in && in->net);
667+
// oassert(in->net->num_driver_pins == 1);
668+
669+
// npin_t* d = in->net->driver_pins[0]; //d is the driver pin to in
670+
// oassert(d && d->node);
671+
// char* role;
672+
// if(d->node && d->node->name && strstr(d->node->name, "adder")){
673+
// if(d->pin_node_idx == 0) role = "cout";
674+
// else if(d->pin_node_idx == 1) role = "sum";
675+
// else role = "?";
676+
// }
677+
// fprintf(stderr, " -> driven by %s pin %d (%s)\n",
678+
// d->node->name ? d->node->name : "(noname)",
679+
// d->pin_node_idx,
680+
// role);
681+
// }
682+
683+
// oassert(netlist->num_top_output_nodes == 5);
684+
// for (int k = 0; k < 5; ++k) {
685+
// nnode_t* po = netlist->top_output_nodes[k];
686+
// oassert(po && po->num_input_pins >= 1);
687+
// npin_t* in = po->input_pins[0];
688+
// oassert(in && in->net && in->net->num_driver_pins == 1);
689+
690+
// // Optional: ensure the driver is the expected slice pin:
691+
// npin_t* drv = in->net->driver_pins[0];
692+
// oassert(drv && drv->node);
693+
// // k=0..3 → slice [offset+k] pin1 (sumout), k=4 → tail pin1 (sumout)
694+
// }
695+
696+
//Create 1-to-1 identity node between drivers of PO nets and PO nodes to allow ABC to see POs
697+
// for (int i = 0; i < netlist->num_top_output_nodes; i++) {
698+
// nnode_t* po_node = netlist->top_output_nodes[i];
699+
// oassert(po_node && po_node->num_input_pins >= 1);
700+
// npin_t* po_in = po_node->input_pins[0];
701+
// oassert(po_in && po_in->net);
702+
// nnet_t* po_net = po_in->net;
703+
// oassert(po_net->num_driver_pins == 1);
704+
// npin_t* po_driver = po_net->driver_pins[0];
705+
// const char* out_name = po_net->name ? po_net->name : "out";
706+
707+
// nnet_t* id_net = allocate_nnet();
708+
// id_net->name = append_string("", "%s_id_net", out_name);
709+
710+
// remap_pin_to_new_net(po_driver, id_net);
711+
712+
// //identity node
713+
// nnode_t* id_node = make_1port_gate(BUF_NODE, 1, 1, po_node, (short)-1);
714+
// id_node->name = append_string("", "%s_abc_anchor", out_name);
715+
// npin_t* id_in = allocate_npin();
716+
// add_input_pin_to_node(id_node, id_in, 0);
717+
// add_fanout_pin_to_net(id_net, id_in);
718+
// npin_t* id_out = allocate_npin();
719+
// add_output_pin_to_node(id_node, id_out, 0);
720+
// add_driver_pin_to_net(po_net, id_out);
721+
722+
// oassert(id_net->num_driver_pins == 1);
723+
// oassert(po_net->num_driver_pins == 1);
724+
// }
725+
// for (int i = 0; i < netlist->num_top_output_nodes; i++) {
726+
// nnode_t* po_node = netlist->top_output_nodes[i];
727+
// oassert(po_node && po_node->num_input_pins >= 1);
728+
// npin_t* po_in = po_node->input_pins[0];
729+
// oassert(po_in && po_in->net);
730+
// nnet_t* po_net = po_in->net;
731+
// oassert(po_net->num_driver_pins == 1);
732+
// npin_t* po_driver = po_net->driver_pins[0];
733+
// const char* out_name = po_net->name ? po_net->name : "out";
734+
735+
// nnet_t* id_net = allocate_nnet();
736+
// id_net->name = append_string("", "%s_id_net", out_name);
737+
738+
// remap_pin_to_new_net(po_driver, id_net);
739+
740+
// //identity NOT nodes
741+
// nnode_t* n1 = make_not_gate(po_node, (short)-1);
742+
// n1->name = append_string("", "%s_abc_anchor_n1", out_name);
743+
744+
// nnet_t* id_net2 = allocate_nnet();
745+
// id_net2->name = append_string("", "%s_id_net2", out_name);
746+
747+
// npin_t* n1_in = allocate_npin(); add_input_pin_to_node(n1, n1_in, 0); add_fanout_pin_to_net(id_net, n1_in);
748+
// npin_t* n1_out = allocate_npin(); add_output_pin_to_node(n1, n1_out, 0); add_driver_pin_to_net(id_net2, n1_out);
749+
750+
// // 3) Second NOT: id_net2 -> n2 -> po_net (n2 becomes the new driver of po_net)
751+
// nnode_t* n2 = make_not_gate(po_node, (short)-1);
752+
// n2->name = append_string("", "%s_abc_anchor_n2", out_name);
753+
754+
// npin_t* n2_in = allocate_npin(); add_input_pin_to_node(n2, n2_in, 0); add_fanout_pin_to_net(id_net2, n2_in);
755+
// npin_t* n2_out = allocate_npin(); add_output_pin_to_node(n2, n2_out, 0); add_driver_pin_to_net(po_net, n2_out);
756+
757+
// // 4) Sanity
758+
// oassert(id_net->num_driver_pins == 1);
759+
// oassert(id_net2->num_driver_pins == 1);
760+
// oassert(po_net->num_driver_pins == 1);
761+
// oassert(po_net->driver_pins[0]->node == n2);
762+
// }
763+
764+
601765
/* Freeing the old node! */
602766
cleanup_sub_old_node(nodeo, netlist);
603767

604768
vtr::free(node);
605769
vtr::free(not_node);
606770
return;
607771
}
608-
609772
/*-------------------------------------------------------------------------
610773
* (function: iterate_adders_for_sub)
611774
*

‎parmys/parmys-plugin/parmys.cc‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -817,6 +817,17 @@ struct ParMYSPass : public Pass {
817817
log("\nTechmap Time: ");
818818
log_time(techmap_time);
819819
log("\n--------------------------------------------------------------------\n");
820+
821+
fprintf(stderr, "[BLIF-OUT] POs=%d\n", odin_netlist->num_top_output_nodes);
822+
for (int k=0; k<odin_netlist->num_top_output_nodes; ++k) {
823+
npin_t* in = odin_netlist->top_output_nodes[k]->input_pins[0];
824+
fprintf(stderr, " PO[%d]: net=%s driver=%s.pin%d\n",
825+
k,
826+
in->net && in->net->name ? in->net->name : "(noname)",
827+
(in->net && in->net->driver_pins[0]->node &&
828+
in->net->driver_pins[0]->node->name) ? in->net->driver_pins[0]->node->name : "(null)",
829+
in->net ? in->net->driver_pins[0]->pin_node_idx : -1);
830+
}
820831
}
821832

822833
static void report(netlist_t *odin_netlist)

‎vtr_flow/misc/yosys/synthesis.tcl‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -80,12 +80,16 @@ techmap -map +/parmys/aldffe2dff.v
8080

8181
opt -full
8282

83+
write_verilog -noexpr pre_parmys.v
84+
8385
# Separate options for Parmys execution (Verilog or SystemVerilog)
8486
if {$env(PARSER) == "default" || $env(PARSER) == "slang"} {
8587
# For Verilog, use -nopass for a simpler, faster flow
8688
parmys -a QQQ -nopass -c CCC YYY
8789
}
8890

91+
write_verilog -noexpr post_parmys.v
92+
8993
opt -full
9094

9195
techmap
@@ -99,4 +103,6 @@ stat
99103

100104
hierarchy -check -auto-top -purge_lib
101105

106+
write_verilog -noexpr post_everything.v
107+
102108
write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ

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