diff --git a/.github/workflows/nightly_test_manual.yml b/.github/workflows/nightly_test_manual.yml index 321be2c2464..656670bb32b 100644 --- a/.github/workflows/nightly_test_manual.yml +++ b/.github/workflows/nightly_test_manual.yml @@ -51,6 +51,7 @@ jobs: ./dev/upgrade_vtr_archs.sh make get_symbiflow_benchmarks make get_zeroasic_rr_graphs + make get_flat_placements # Build VTR using the default build options. - name: 'Build VTR' diff --git a/CMakeLists.txt b/CMakeLists.txt index 47cdef240b4..ef51799e39e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -368,6 +368,14 @@ add_custom_target(get_zeroasic_rr_graphs WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} COMMENT "Downloading (~2MB) and extracting Zero ASIC RR graphs (~0.1GB) into VTR source tree.") +# +# Flat Placement Files +# +add_custom_target(get_flat_placements + COMMAND ./vtr_flow/scripts/get_flat_placement_files.py --vtr_flow_dir ./vtr_flow + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + COMMENT "Downloading (~5MB) and extracting Flat Placement Files (~0.1GB) into VTR source tree.") + # # Unit Testing # diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index 97d671f5f29..092fd2a3f88 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -444,22 +444,22 @@ Use the options below to override this default naming behaviour. Reads a file containing the locations of each atom on the FPGA. This is used by the packer to better cluster atoms together. - The flat placement file (which often ends in ``.fplace``) is a text file + The flat placement file (which often ends in :ref:`.fplace `) is a text file where each line describes the location of an atom. Each line in the flat placement file should have the following syntax: .. code-block:: none - + For example: .. code-block:: none - n523 6 8 0 0 3 - n522 6 8 0 0 5 - n520 6 8 0 0 2 - n518 6 8 0 0 16 + n523 6 8 0 0 + n522 6 8 0 0 + n520 6 8 0 0 + n518 6 8 0 0 The position of the atom on the FPGA is given by 3 floating point values (``x``, ``y``, ``layer``). We allow for the positions of atom to be not @@ -475,25 +475,29 @@ Use the options below to override this default naming behaviour. the sub-tile of an atom is unkown (allowing the packing algorithm to choose any sub-tile at the given (x, y, layer) location). - The ``site_idx`` is an optional index into a linearized list of primitive - locations within a cluster-level block which may be used as a hint to - reconstruct clusters. - .. warning:: This interface is currently experimental and under active development. .. option:: --write_flat_place - Writes the post-placement locations of each atom into a flat placement file. + Writes the post-placement locations of each atom into a flat placement file + (see :ref:`flat placement file format `). + + For each atom in the netlist, the following information is stored into the + flat placement file: + + * The x, y, and sub_tile location of the cluster that contains this atom. + +.. option:: --write_legalized_flat_place + + Writes the post-legalization locations of each atom into a flat placement file + (see :ref:`flat placement file format `). For each atom in the netlist, the following information is stored into the flat placement file: * The x, y, and sub_tile location of the cluster that contains this atom. - * The flat site index of this atom in its cluster. The flat site index is a - linearized ID of primitive locations in a cluster. This may be used as a - hint to reconstruct clusters. .. _netlist_options: @@ -1287,7 +1291,7 @@ Analytical Placement is generally split into three stages: **Default:** ``bipartitioning`` -.. option:: --ap_full_legalizer {naive | appack} +.. option:: --ap_full_legalizer {naive | appack | flat-recon} Controls which Full Legalizer to use in the AP Flow. @@ -1295,6 +1299,12 @@ Analytical Placement is generally split into three stages: * ``appack`` Use APPack, which takes the Packer in VPR and uses the flat atom placement to create better clusters. + * ``flat-recon`` Use the Flat Placement Reconstruction Full Legalizer which tries to reconstruct a clustered placement that is + as close to the incoming flat placement as possible. It can be used to read a flat placement from a :ref:`.fplace ` file + or on the (in memory) output of VTR's integrated Global Placement algorithm. In both cases, it expects the given solution to be close to legal. + If used with a :ref:`.fplace ` file, each atom in a molecule should have compatible location information. It is legal to + leave some molecules unconstrained; the reconstruction phase will choose where to place them but does not attempt to optimize these locations. + **Default:** ``appack`` .. option:: --ap_detailed_placer {none | annealer} diff --git a/doc/src/vpr/file_formats.rst b/doc/src/vpr/file_formats.rst index 32fbb0dfc93..54ba00a1ea3 100644 --- a/doc/src/vpr/file_formats.rst +++ b/doc/src/vpr/file_formats.rst @@ -696,6 +696,42 @@ Placement File Format Example xor5 1 2 0 0 #6 [1] 1 1 0 1 #7 +.. _vpr_flat_place_file: + +Flat Placement File Format (.fplace) +------------------------------------ +The flat placement file is a text file where each line describes the location of +an atom. Each line in the flat placement file should have the following syntax: + +.. code-block:: none + + + +For example: + + .. code-block:: none + + n523 6 8 0 0 + n522 6 8 0 0 + n520 6 9 0 0 + n518 6 9 0 0 + +The position of the atom on the FPGA is given by 3 floating point values +(``x``, ``y``, ``layer``). We allow x and y locations to be off-grid since +this flat placement will be fed into the packer and placer, which will snap +the positions to grid locations. For 2D FPGA architectures, the ``layer`` should be 0. + +The ``sub_tile`` is a clustered placement construct: which cluster-level +location at a given (x, y, layer) should these atoms go at (relevant when +multiple clusters can be stacked there). A sub-tile of -1 may be used when +the sub-tile of an atom is unkown (allowing the packing algorithm to choose +any sub-tile at the given (x, y, layer) location). + +When used with ``flat-recon`` full legalizer (see :option:`vpr --ap_full_legalizer`), +each atom in a molecule should have compatible location information. It is legal to +leave some molecules unconstrained; the reconstruction phase will choose where +to place them but does not attempt to optimize these locations. + .. _vpr_route_file: Routing File Format (.route) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 3f1694f0457..3418e7ba342 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -890,7 +890,40 @@ struct t_physical_tile_loc { operator bool() const { return !(x == ARCH_FPGA_UNDEFINED_VAL || y == ARCH_FPGA_UNDEFINED_VAL || layer_num == ARCH_FPGA_UNDEFINED_VAL); } + + /** + * @brief Comparison operator for t_physical_tile_loc + * + * Tiles are ordered first by layer number, then by x, and finally by y. + */ + friend bool operator<(const t_physical_tile_loc& lhs, const t_physical_tile_loc& rhs) { + if (lhs.layer_num != rhs.layer_num) + return lhs.layer_num < rhs.layer_num; + if (lhs.x != rhs.x) + return lhs.x < rhs.x; + return lhs.y < rhs.y; + } + + friend bool operator==(const t_physical_tile_loc& a, const t_physical_tile_loc& b) { + return a.x == b.x && a.y == b.y && a.layer_num == b.layer_num; + } + + friend bool operator!=(const t_physical_tile_loc& a, const t_physical_tile_loc& b) { + return !(a == b); + } +}; + +namespace std { +template<> +struct hash { + std::size_t operator()(const t_physical_tile_loc& v) const noexcept { + std::size_t seed = std::hash{}(v.x); + vtr::hash_combine(seed, v.y); + vtr::hash_combine(seed, v.layer_num); + return seed; + } }; +} // namespace std /** Describes I/O and clock ports of a physical tile type * diff --git a/vpr/src/analytical_place/analytical_placement_flow.cpp b/vpr/src/analytical_place/analytical_placement_flow.cpp index e54d0166878..6fe4cf27049 100644 --- a/vpr/src/analytical_place/analytical_placement_flow.cpp +++ b/vpr/src/analytical_place/analytical_placement_flow.cpp @@ -18,6 +18,7 @@ #include "gen_ap_netlist_from_atoms.h" #include "global_placer.h" #include "globals.h" +#include "load_flat_place.h" #include "netlist_fwd.h" #include "partial_legalizer.h" #include "partial_placement.h" @@ -80,6 +81,7 @@ static void print_ap_netlist_stats(const APNetlist& netlist) { * to be generated on ap_netlist or have the same blocks. */ static void convert_flat_to_partial_placement(const FlatPlacementInfo& flat_placement_info, const APNetlist& ap_netlist, const Prepacker& prepacker, PartialPlacement& p_placement) { + size_t num_mols_assigned_to_center = 0; for (APBlockId ap_blk_id : ap_netlist.blocks()) { // Get the molecule that AP block represents PackMoleculeId mol_id = ap_netlist.block_molecule(ap_blk_id); @@ -97,6 +99,8 @@ static void convert_flat_to_partial_placement(const FlatPlacementInfo& flat_plac float current_loc_layer = flat_placement_info.blk_layer[atom_blk_id]; int current_loc_sub_tile = flat_placement_info.blk_sub_tile[atom_blk_id]; if (found_valid_atom) { + if (current_loc_x == -1 || current_loc_y == -1) + continue; if (current_loc_x != atom_loc_x || current_loc_y != atom_loc_y || current_loc_layer != atom_loc_layer || current_loc_sub_tile != atom_loc_sub_tile) VPR_FATAL_ERROR(VPR_ERROR_AP, "Molecule of ID %zu contains atom %s (ID: %zu) with a location (%g, %g, layer: %g, subtile: %d) " @@ -105,21 +109,53 @@ static void convert_flat_to_partial_placement(const FlatPlacementInfo& flat_plac current_loc_x, current_loc_y, current_loc_layer, current_loc_sub_tile, atom_loc_x, atom_loc_y, atom_loc_layer, atom_loc_sub_tile); } else { - atom_loc_x = current_loc_x; - atom_loc_y = current_loc_y; - atom_loc_layer = current_loc_layer; - atom_loc_sub_tile = current_loc_sub_tile; - found_valid_atom = true; + if (current_loc_x != -1 && current_loc_y != -1) { + atom_loc_x = std::clamp(current_loc_x, 0.0f, + static_cast(g_vpr_ctx.device().grid.width() -1)); + atom_loc_y = std::clamp(current_loc_y, 0.0f, + static_cast(g_vpr_ctx.device().grid.height() -1)); + // If current_loc_layer or current_loc_sub_tile are unset (-1), default to layer 0 and sub_tile 0. + if (current_loc_layer == -1) + current_loc_layer = 0; + if (current_loc_sub_tile == -1) + current_loc_sub_tile = 0; + atom_loc_layer = current_loc_layer; + atom_loc_sub_tile = current_loc_sub_tile; + found_valid_atom = true; + } } } - // Ensure that there is a valid atom in the molecule to pass its location. - VTR_ASSERT_MSG(found_valid_atom, "Each molecule must contain at least one valid atom"); - // Pass the placement information - p_placement.block_x_locs[ap_blk_id] = atom_loc_x; - p_placement.block_y_locs[ap_blk_id] = atom_loc_y; - p_placement.block_layer_nums[ap_blk_id] = atom_loc_layer; - p_placement.block_sub_tiles[ap_blk_id] = atom_loc_sub_tile; + // If any atom in the molecule has a location assigned, use that location + // for the entire AP block. Otherwise, assign the AP block to the center + // of the device grid and update the flat placement info for all its atoms accordingly. + if (!found_valid_atom) { + num_mols_assigned_to_center++; + VTR_LOG_WARN("No atoms of molecule ID %zu provided in the flat placement. Assigning it to the device center.\n", mol_id); + p_placement.block_x_locs[ap_blk_id] = g_vpr_ctx.device().grid.width() / 2.0f; + p_placement.block_y_locs[ap_blk_id] = g_vpr_ctx.device().grid.height() / 2.0f; + p_placement.block_layer_nums[ap_blk_id] = 0; + p_placement.block_sub_tiles[ap_blk_id] = 0; + // Update flat placement for atoms of that molecule accordingly. + // Needed for flat placement reconstruction statistics reporting. + for (AtomBlockId atom_blk_id : mol.atom_block_ids) { + g_vpr_ctx.mutable_atom().mutable_flat_placement_info().blk_x_pos[atom_blk_id] = g_vpr_ctx.device().grid.width() / 2.0f; + g_vpr_ctx.mutable_atom().mutable_flat_placement_info().blk_y_pos[atom_blk_id] = g_vpr_ctx.device().grid.height() / 2.0f; + g_vpr_ctx.mutable_atom().mutable_flat_placement_info().blk_layer[atom_blk_id] = 0; + g_vpr_ctx.mutable_atom().mutable_flat_placement_info().blk_sub_tile[atom_blk_id] = 0; + } + // TODO: If an atom's location is specified in the placement constraints, + // verify it matches the assigned flat placement. If not, override the + // flat placement with the constraint location and warn the user. + } else { + // Pass the placement information + p_placement.block_x_locs[ap_blk_id] = atom_loc_x; + p_placement.block_y_locs[ap_blk_id] = atom_loc_y; + p_placement.block_layer_nums[ap_blk_id] = atom_loc_layer; + p_placement.block_sub_tiles[ap_blk_id] = atom_loc_sub_tile; + } } + VTR_LOG("%zu of %zu molecules placed at device center (no atoms of these molecules found in flat placement).\n", + num_mols_assigned_to_center, ap_netlist.blocks().size()); } /** @@ -245,6 +281,15 @@ void run_analytical_placement_flow(t_vpr_setup& vpr_setup) { // Print the device utilization print_device_utilization(target_device_utilization); + // Write out a flat placement file at the end of Full Legalization if the + // option is specified. + if (!vpr_setup.FileNameOpts.write_legalized_flat_place_file.empty()) { + write_flat_placement(vpr_setup.FileNameOpts.write_legalized_flat_place_file.c_str(), + g_vpr_ctx.clustering().clb_nlist, + g_vpr_ctx.placement().block_locs(), + g_vpr_ctx.clustering().atoms_lookup); + } + // Run the Detailed Placer. std::unique_ptr detailed_placer = make_detailed_placer(ap_opts.detailed_placer_type, g_vpr_ctx.placement().blk_loc_registry(), diff --git a/vpr/src/analytical_place/ap_flow_enums.h b/vpr/src/analytical_place/ap_flow_enums.h index f147fd953dc..e9b99160ffb 100644 --- a/vpr/src/analytical_place/ap_flow_enums.h +++ b/vpr/src/analytical_place/ap_flow_enums.h @@ -39,9 +39,9 @@ enum class e_ap_partial_legalizer { * enum can select between these different Full Legalizers. */ enum class e_ap_full_legalizer { - Naive, ///< The Naive Full Legalizer, which clusters atoms placed in the same tile and tries to place them in that tile according to the flat placement. - APPack, ///< The APPack Full Legalizer, which uses the flat placement to improve the Packer and Placer. - Basic_Min_Disturbance ///< The Basic Min. Disturbance Full Legalizer, which tries to reconstruct a clustered placement that is as close to the incoming flat placement as it can. + Naive, ///< The Naive Full Legalizer, which clusters atoms placed in the same tile and tries to place them in that tile according to the flat placement. + APPack, ///< The APPack Full Legalizer, which uses the flat placement to improve the Packer and Placer. + FlatRecon ///< The Flat Placement Reconstruction Full Legalizer, which tries to reconstruct a clustered placement (or the in-memory global placement) that is as close to the incoming flat placement as it can. }; /** diff --git a/vpr/src/analytical_place/full_legalizer.cpp b/vpr/src/analytical_place/full_legalizer.cpp index fcfd5848298..d18138f5228 100644 --- a/vpr/src/analytical_place/full_legalizer.cpp +++ b/vpr/src/analytical_place/full_legalizer.cpp @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -35,6 +36,7 @@ #include "pack.h" #include "partial_placement.h" #include "physical_types.h" +#include "physical_types_util.h" #include "place.h" #include "place_and_route.h" #include "place_constraints.h" @@ -55,6 +57,10 @@ #include "vtr_time.h" #include "vtr_vector.h" +#include "setup_grid.h" +#include "stats.h" + + std::unique_ptr make_full_legalizer(e_ap_full_legalizer full_legalizer_type, const APNetlist& ap_netlist, const AtomNetlist& atom_netlist, @@ -80,11 +86,14 @@ std::unique_ptr make_full_legalizer(e_ap_full_legalizer full_lega vpr_setup, arch, device_grid); - case e_ap_full_legalizer::Basic_Min_Disturbance: - VTR_LOG("Basic Minimum Disturbance Full Legalizer selected!\n"); - VPR_FATAL_ERROR(VPR_ERROR_AP, - "Basic Min. Disturbance Full Legalizer has not been implemented yet."); - + case e_ap_full_legalizer::FlatRecon: + return std::make_unique(ap_netlist, + atom_netlist, + prepacker, + pre_cluster_timing_manager, + vpr_setup, + arch, + device_grid); default: VPR_FATAL_ERROR(VPR_ERROR_AP, "Unrecognized full legalizer type"); @@ -281,6 +290,722 @@ static LegalizationClusterId create_new_cluster(PackMoleculeId seed_molecule_id, return LegalizationClusterId(); } +/** + * @brief Get the logical block type of a given molecule. + * + * @param mol_id The molecule id to get its logical block type. + * @param prepacker The prepacker used to get molecule from its id. + * @param primitive_candidate_block_types Candidate logical block types for the given molecule. + * + */ +static t_logical_block_type_ptr infer_molecule_logical_block_type(PackMoleculeId mol_id, + const Prepacker& prepacker, + const vtr::vector>& primitive_candidate_block_types) { + // Get the root atom and its model id. Ensure that both is valid. + const AtomContext& atom_ctx = g_vpr_ctx.atom(); + const t_pack_molecule& molecule = prepacker.get_molecule(mol_id); + AtomBlockId root_atom = molecule.atom_block_ids[molecule.root]; + VTR_ASSERT(root_atom.is_valid()); + LogicalModelId root_model_id = atom_ctx.netlist().block_model(root_atom); + VTR_ASSERT(root_model_id.is_valid()); + + // Get the first candidate type. + const auto& candidate_types = primitive_candidate_block_types[root_model_id]; + if (!candidate_types.empty()) { + return candidate_types.front(); + } + + // A valid block type should have been found at that point. + VPR_FATAL_ERROR(VPR_ERROR_AP, "Could not determine block type for molecule ID %zu\n", size_t(mol_id)); +} + +std::unordered_map> +FlatRecon::sort_and_group_blocks_by_tile(const PartialPlacement& p_placement) { + vtr::ScopedStartFinishTimer pack_reconstruction_timer("Sorting and Grouping Blocks by Tile"); + // Block sorting information. This can be altered easily to try different sorting strategies. + struct BlockInformation { + PackMoleculeId mol_id; + int ext_inps; + bool is_long_chain; + t_physical_tile_loc tile_loc; + }; + + // Collect the sorting information and tile information. + std::vector sorted_blocks; + sorted_blocks.reserve(ap_netlist_.blocks().size()); + for (APBlockId blk_id : ap_netlist_.blocks()) { + PackMoleculeId mol_id = ap_netlist_.block_molecule(blk_id); + const auto& mol = prepacker_.get_molecule(mol_id); + + int num_ext_inputs = prepacker_.calc_molecule_stats(mol_id, atom_netlist_, arch_.models).num_used_ext_inputs; + bool long_chain = mol.is_chain() && prepacker_.get_molecule_chain_info(mol.chain_id).is_long_chain; + t_physical_tile_loc tile_loc = p_placement.get_containing_tile_loc(blk_id); + + sorted_blocks.push_back({mol_id, num_ext_inputs, long_chain, tile_loc}); + } + + // Sort the blocks so that: + // 1) Long carry-chain molecules are placed first. They have strict placement + // constraints, so we want to place them before the layout becomes constrained + // by other blocks. This will avoid increasing the displacement. + // 2) Within the same category (both long-chain or both non-long-chain), sort + // by descending number of external input pins. (empirically best for reconstructing + // dense clusters compared to external outputs or external total pins). + std::sort(sorted_blocks.begin(), sorted_blocks.end(), + [](const BlockInformation& a, const BlockInformation& b) { + // Long chains should always come before non-long chains + if (a.is_long_chain && !b.is_long_chain) + return true; + if (!a.is_long_chain && b.is_long_chain) + return false; + + // If both blocks are chains / not chains, sort in decreasing order of external inputs. + return a.ext_inps > b.ext_inps; + }); + + // Group the molecules by root tile. Any non-zero offset gets + // pulled back to its root. + std::unordered_map> tile_blocks; + mol_desired_physical_tile_loc.reserve(ap_netlist_.blocks().size()); + for (const auto& [mol_id, ext_pins, is_long_chain, tile_loc] : sorted_blocks) { + int width_offset = device_grid_.get_width_offset(tile_loc); + int height_offset = device_grid_.get_height_offset(tile_loc); + t_physical_tile_loc root_loc = {tile_loc.x - width_offset, + tile_loc.y - height_offset, + tile_loc.layer_num}; + tile_blocks[root_loc].push_back(mol_id); + mol_desired_physical_tile_loc[mol_id] = root_loc; + } + + return tile_blocks; +} + +std::unordered_set +FlatRecon::cluster_molecules_in_tile(const t_physical_tile_loc& tile_loc, + const t_physical_tile_type_ptr& tile_type, + const std::vector& tile_molecules, + ClusterLegalizer& cluster_legalizer, + const vtr::vector>& primitive_candidate_block_types) { + std::unordered_set created_clusters; + for (PackMoleculeId mol_id : tile_molecules) { + // Get the block type for compatibility check. + t_logical_block_type_ptr block_type = infer_molecule_logical_block_type(mol_id, prepacker_, primitive_candidate_block_types); + + // Go over all subtiles at this tile, trying to insert each molecule that + // is supposed to be in that tile in the first existing cluster that can + // accommodate it; if none can, create a new cluster if there is a subtile + // that has no cluster yet. + for (int sub_tile = 0; sub_tile < tile_type->capacity; ++sub_tile) { + const t_pl_loc loc{tile_loc.x, tile_loc.y, sub_tile, tile_loc.layer_num}; + auto cluster_it = loc_to_cluster_id_placed.find(loc); + + if (cluster_it != loc_to_cluster_id_placed.end()) { + // Try adding to the existing cluster + LegalizationClusterId cluster_id = cluster_it->second; + if (!cluster_legalizer.is_molecule_compatible(mol_id, cluster_id)) + continue; + + e_block_pack_status pack_status = cluster_legalizer.add_mol_to_cluster(mol_id, cluster_id); + if (pack_status == e_block_pack_status::BLK_PASSED) + break; + } else if (is_tile_compatible(tile_type, block_type)) { + // Create new cluster + LegalizationClusterId new_id = create_new_cluster(mol_id, prepacker_, cluster_legalizer, primitive_candidate_block_types); + created_clusters.insert(new_id); + cluster_locs[new_id] = loc; + loc_to_cluster_id_placed[loc] = new_id; + tile_clusters_matrix[tile_loc.layer_num][tile_loc.x][tile_loc.y].insert(new_id); + break; + } + } + } + return created_clusters; +} + +void FlatRecon::self_clustering(ClusterLegalizer& cluster_legalizer, + const DeviceGrid& device_grid, + const vtr::vector>& primitive_candidate_block_types, + std::unordered_map>& tile_blocks) { + vtr::ScopedStartFinishTimer reconstruction_pass_clustering("Reconstruction Pass Clustering"); + for (const auto& [tile_loc, tile_molecules] : tile_blocks) { + // Get tile type of current tile location. + const t_physical_tile_type_ptr tile_type = device_grid.get_physical_type(tile_loc); + + // Try to create clusters with fast strategy checking the compatibility + // with tile and its capacity. Store the cluster ids to check their legality. + cluster_legalizer.set_legalization_strategy(ClusterLegalizationStrategy::SKIP_INTRA_LB_ROUTE); + std::unordered_set created_clusters = cluster_molecules_in_tile(tile_loc, + tile_type, + tile_molecules, + cluster_legalizer, + primitive_candidate_block_types); + // Check legality of clusters created with fast pass. Store the + // illegal cluster molecules for full strategy pass. + std::vector illegal_cluster_mols; + for (LegalizationClusterId cluster_id: created_clusters) { + if (!cluster_legalizer.check_cluster_legality(cluster_id)) { + for (PackMoleculeId mol_id : cluster_legalizer.get_cluster_molecules(cluster_id)) { + illegal_cluster_mols.push_back(mol_id); + } + // Erase related data of illegal cluster + loc_to_cluster_id_placed.erase(cluster_locs[cluster_id]); + cluster_legalizer.destroy_cluster(cluster_id); + tile_clusters_matrix[tile_loc.layer_num][tile_loc.x][tile_loc.y].erase(cluster_id); + } else { + cluster_legalizer.clean_cluster(cluster_id); + } + } + + // If there are any illegal molecules, set the legalization strategy to + // full and try to cluster the unclustered molecules in same tile again. + if (!illegal_cluster_mols.empty()) { + cluster_legalizer.set_legalization_strategy(ClusterLegalizationStrategy::FULL); + created_clusters = cluster_molecules_in_tile(tile_loc, + tile_type, + illegal_cluster_mols, + cluster_legalizer, + primitive_candidate_block_types); + // Clean clusters created with full strategy not to increase memory footprint. + for (LegalizationClusterId cluster_id : created_clusters) { + cluster_legalizer.clean_cluster(cluster_id); + } + } + } +} + +std::unordered_set +FlatRecon::neighbor_clustering(ClusterLegalizer& cluster_legalizer, + const vtr::vector>& primitive_candidate_block_types) { + vtr::ScopedStartFinishTimer neigh_pass_clustering("Neighbor Pass Clustering"); + + // Iterate over molecules and try to join the unclustered ones to their + // already created 8-neighboring tile clusters. + std::unordered_set mols_clustered; + for (APBlockId blk_id : ap_netlist_.blocks()) { + // Get unclustered block and its location. + PackMoleculeId molecule_id = ap_netlist_.block_molecule(blk_id); + t_physical_tile_loc loc = mol_desired_physical_tile_loc[molecule_id]; + + // Skip the already clustered molecules. + if (cluster_legalizer.is_mol_clustered(molecule_id)) + continue; + + // Get 8-neighbouring tile locations of the current molecule in the same layer and same type. + std::vector neighbor_tile_locs; + neighbor_tile_locs.reserve(8); + auto [layers, width, height] = device_grid_.dim_sizes(); + for (int dx : {-1, 0, 1}) { + for (int dy : {-1, 0, 1}) { + if (dx == 0 && dy == 0) continue; + int neighbor_x = loc.x + dx, neighbor_y = loc.y + dy; + if (neighbor_x < 0 || neighbor_x >= (int)width || neighbor_y < 0 || neighbor_y >= (int)height) + continue; + if (device_grid_.get_physical_type(loc) != device_grid_.get_physical_type({neighbor_x, neighbor_y, loc.layer_num})) + continue; + neighbor_tile_locs.push_back({neighbor_x, neighbor_y, loc.layer_num}); + } + } + + // Get the average molecule count in each neighbor tile location. + // Also remove empty neighbor tiles from neighbor_tile_locs. + std::unordered_map avg_mols_in_tile; + avg_mols_in_tile.reserve(neighbor_tile_locs.size()); + for (auto it = neighbor_tile_locs.begin(); it != neighbor_tile_locs.end(); ) { + const std::unordered_set& clusters = tile_clusters_matrix[it->layer_num][it->x][it->y]; + if (clusters.empty()) { + it = neighbor_tile_locs.erase(it); + continue; + } + size_t total_molecules_in_tile = 0; + for (const LegalizationClusterId& cluster_id: clusters) { + total_molecules_in_tile += cluster_legalizer.get_num_molecules_in_cluster(cluster_id); + } + avg_mols_in_tile[*it] = double(total_molecules_in_tile) / clusters.size(); + ++it; + } + + // Sort tile locations by increasing average molecule count. + std::sort(neighbor_tile_locs.begin(), neighbor_tile_locs.end(), + [&](const t_physical_tile_loc& a, const t_physical_tile_loc& b) { + return avg_mols_in_tile[a] < avg_mols_in_tile[b]; + }); + + // Try to fit the unclustered molecule to sorted neighbor tile clusters. + // Note: This pass opens a cluster, try to add one molecule to it, then close it again. This might cost CPU + // time if many molecules are packed in the same cluster in this pass, vs. just opening it once and adding + // them all. + bool fit_in_a_neighbor = false; + for (const t_physical_tile_loc& neighbor_tile_loc: neighbor_tile_locs) { + // Get the current neighbor tile clusters. + std::unordered_set& clusters = tile_clusters_matrix[neighbor_tile_loc.layer_num][neighbor_tile_loc.x][neighbor_tile_loc.y]; + + // Iterate over the current tile clusters until unclustered molecule fit in one. + for (auto it = clusters.begin(); it != clusters.end() && !fit_in_a_neighbor; ) { + LegalizationClusterId cluster_id = *it; + if (!cluster_id.is_valid()) { + ++it; + continue; + } + + // Get the cluster molecules and destroy the old cluster. + std::vector cluster_molecules = cluster_legalizer.get_cluster_molecules(cluster_id); + cluster_legalizer.destroy_cluster(cluster_id); + + // Set the legalization strategy to speculative for fast try. + cluster_legalizer.set_legalization_strategy(ClusterLegalizationStrategy::SKIP_INTRA_LB_ROUTE); + + // Use the first molecule as seed to recreate the cluster. + PackMoleculeId seed_mol = cluster_molecules[0]; + LegalizationClusterId new_cluster_id = create_new_cluster(seed_mol, prepacker_, cluster_legalizer, primitive_candidate_block_types); + + // Add remaining old molecules to the new cluster. + for (PackMoleculeId mol_id: cluster_molecules) { + if (mol_id == seed_mol) + continue; + if (!cluster_legalizer.is_molecule_compatible(mol_id, new_cluster_id)) + continue; + cluster_legalizer.add_mol_to_cluster(mol_id, new_cluster_id); + } + + // Set the legalization strategy to full for adding new unclustered molecule. + // Also if recreated clusters if illegal, try to create with full strategy. + cluster_legalizer.set_legalization_strategy(ClusterLegalizationStrategy::FULL); + + // If recreated cluster is illegal, try again with full strategy. + if (!cluster_legalizer.check_cluster_legality(new_cluster_id)) { + cluster_legalizer.destroy_cluster(new_cluster_id); + new_cluster_id = create_new_cluster(seed_mol, prepacker_, cluster_legalizer, primitive_candidate_block_types); + for (PackMoleculeId mol_id: cluster_molecules) { + if (mol_id == seed_mol) + continue; + if (!cluster_legalizer.is_molecule_compatible(mol_id, new_cluster_id)) + continue; + cluster_legalizer.add_mol_to_cluster(mol_id, new_cluster_id); + } + } + + // Lastly, try to add the new unclustered molecule to the recreated cluster. + if (cluster_legalizer.is_molecule_compatible(molecule_id, new_cluster_id)){ + e_block_pack_status pack_status = cluster_legalizer.add_mol_to_cluster(molecule_id, new_cluster_id); + if (pack_status == e_block_pack_status::BLK_PASSED) + fit_in_a_neighbor = true; + } + + // Clean the new cluster to avoid increasing memory footprint. + cluster_legalizer.clean_cluster(new_cluster_id); + + // Erase old cluster id and add new one. + it = clusters.erase(it); + clusters.insert(new_cluster_id); + } + // Stop iterating neighbor tiles if current molecule already fit in a neighbor cluster. + if (fit_in_a_neighbor) { + mols_clustered.insert(molecule_id); + break; + } + } + } + return mols_clustered; +} + +std::unordered_set +FlatRecon::orphan_window_clustering(ClusterLegalizer& cluster_legalizer, + const vtr::vector>& primitive_candidate_block_types, + int search_radius) { + std::string timer_label = "Orphan Window Clustering with search radius " + std::to_string(search_radius); + vtr::ScopedStartFinishTimer orphan_window_clustering(timer_label); + + // Create unclustered blocks spatial data. It stores a vector of molecules ids + // for each tile location of [layer][x][y]. + auto [layer_num, width, height] = device_grid_.dim_sizes(); + vtr::NdMatrix, 3> unclustered_tile_molecules({layer_num, width, height}); + std::vector unclustered_blocks; + for (APBlockId blk_id: ap_netlist_.blocks()) { + PackMoleculeId mol_id = ap_netlist_.block_molecule(blk_id); + if (cluster_legalizer.is_mol_clustered(mol_id)) + continue; + t_physical_tile_loc tile_loc = mol_desired_physical_tile_loc[mol_id]; + unclustered_tile_molecules[tile_loc.layer_num][tile_loc.x][tile_loc.y].insert(mol_id); + unclustered_blocks.push_back(mol_id); + } + + // Sort unclustered blocks by highest external input pins. + std::sort(unclustered_blocks.begin(), unclustered_blocks.end(), + [this](const PackMoleculeId& a, const PackMoleculeId& b) { + int ext_pins_a = prepacker_.calc_molecule_stats(a, atom_netlist_, arch_.models).num_used_ext_inputs; + int ext_pins_b = prepacker_.calc_molecule_stats(b, atom_netlist_, arch_.models).num_used_ext_inputs; + return ext_pins_a > ext_pins_b; + }); + + std::unordered_set created_clusters; + for (PackMoleculeId seed_mol_id: unclustered_blocks) { + if (cluster_legalizer.is_mol_clustered(seed_mol_id)) + continue; + + // Start the new cluster with seed molecule using full strategy. + // Note: This could waste time vs. using the fast strategy first and falling back + // to full, but currently orphan clustering doesn't take that long as few molecules are clustered. + cluster_legalizer.set_legalization_strategy(ClusterLegalizationStrategy::FULL); + LegalizationClusterId cluster_id = create_new_cluster(seed_mol_id, prepacker_, cluster_legalizer, primitive_candidate_block_types); + created_clusters.insert(cluster_id); + + // Get the physical tile location of the current molecules and delete + // the seed molecule from unclustered search data. + t_physical_tile_loc seed_tile_loc = mol_desired_physical_tile_loc[seed_mol_id]; + unclustered_tile_molecules[seed_tile_loc.layer_num][seed_tile_loc.x][seed_tile_loc.y].erase(seed_mol_id); + + // Keep track of the visited tile locations. + vtr::NdMatrix visited({layer_num, width, height}, false); + std::queue loc_queue; + loc_queue.push(seed_tile_loc); + + while(!loc_queue.empty()) { + // Get the first location and try to add molecules in that tile to cluster created with seed molecule. + t_physical_tile_loc current_tile_loc = loc_queue.front(); + loc_queue.pop(); + + // Skip this location if it is already visited. + if (visited[current_tile_loc.layer_num][current_tile_loc.x][current_tile_loc.y]) + continue; + visited[current_tile_loc.layer_num][current_tile_loc.x][current_tile_loc.y] = true; + + // Skip this location if it is out of our range. This will stop expanding beyond scope. + int distance = std::abs(seed_tile_loc.x - current_tile_loc.x) + std::abs(seed_tile_loc.y - current_tile_loc.y) + std::abs(seed_tile_loc.layer_num - current_tile_loc.layer_num); + if (distance> search_radius) + continue; + + // Try to add each unclustered molecule in that tile to the current cluster. + std::unordered_set& tile_molecules = unclustered_tile_molecules[current_tile_loc.layer_num][current_tile_loc.x][current_tile_loc.y]; + for (auto it = tile_molecules.begin(); it != tile_molecules.end(); ) { + if (!cluster_legalizer.is_molecule_compatible(*it, cluster_id)) { + ++it; + continue; + } + if (cluster_legalizer.add_mol_to_cluster(*it, cluster_id) == e_block_pack_status::BLK_PASSED) { + // If added, remove from unclustered spatial data. + it = tile_molecules.erase(it); + } else { + ++it; + } + } + + // Push the neighbor tile locations onto queue (in the same layer). + // This will push the neighbors left, right, above, and below the current + // location. The code above will check if these locations are already + // been visited or in our search radius. + if (current_tile_loc.x > 0) { + t_physical_tile_loc new_tile_loc = t_physical_tile_loc(current_tile_loc.x - 1, + current_tile_loc.y, + current_tile_loc.layer_num); + loc_queue.push(new_tile_loc); + } + if (current_tile_loc.x < (int)width - 1) { + t_physical_tile_loc new_tile_loc = t_physical_tile_loc(current_tile_loc.x + 1, + current_tile_loc.y, + current_tile_loc.layer_num); + loc_queue.push(new_tile_loc); + } + if (current_tile_loc.y > 0) { + t_physical_tile_loc new_tile_loc = t_physical_tile_loc(current_tile_loc.x, + current_tile_loc.y - 1, + current_tile_loc.layer_num); + loc_queue.push(new_tile_loc); + } + if (current_tile_loc.y < (int)height - 1) { + t_physical_tile_loc new_tile_loc = t_physical_tile_loc(current_tile_loc.x, + current_tile_loc.y + 1, + current_tile_loc.layer_num); + loc_queue.push(new_tile_loc); + } + } + // Clean the new created cluster to avoid memory footprint increase. + cluster_legalizer.clean_cluster(cluster_id); + } + return created_clusters; +} + +void FlatRecon::report_clustering_summary(ClusterLegalizer& cluster_legalizer, + std::unordered_set& neighbor_pass_molecules, + std::unordered_set& orphan_window_clusters) { + // Define stat collection variables: key is a block_type string and value + // is the number of clusters of that type created. + std::unordered_map cluster_type_count_self_pass, + cluster_type_count_orphan_window_pass; + size_t num_of_mols_clustered_in_self_pass = 0, + num_of_mols_clustered_in_orphan_window_pass = 0; + size_t num_of_clusters_in_self_pass = 0, + num_of_clusters_in_orphan_window_pass = 0; + + // Collect statistics. + for (LegalizationClusterId cluster_id : cluster_legalizer.clusters()) { + if (!cluster_id.is_valid()) continue; + + t_logical_block_type_ptr block_type = cluster_legalizer.get_cluster_type(cluster_id); + std::string block_name = block_type->name; + + if (orphan_window_clusters.count(cluster_id)) { + num_of_clusters_in_orphan_window_pass++; + num_of_mols_clustered_in_orphan_window_pass += cluster_legalizer.get_cluster_molecules(cluster_id).size(); + cluster_type_count_orphan_window_pass[block_name]++; + } else { + num_of_clusters_in_self_pass++; + num_of_mols_clustered_in_self_pass += cluster_legalizer.get_cluster_molecules(cluster_id).size(); + cluster_type_count_self_pass[block_name]++; + } + } + + // Note: neighbor-pass molecules were initially counted in 'self' because they + // joined clusters created in the self pass. To report disjoint pass totals, + // remove them from the self-pass count here. + size_t num_of_mols_clustered_in_neighbor_pass = neighbor_pass_molecules.size(); + num_of_mols_clustered_in_self_pass -= num_of_mols_clustered_in_neighbor_pass; + + size_t total_mols_clustered = num_of_mols_clustered_in_self_pass + num_of_mols_clustered_in_neighbor_pass + num_of_mols_clustered_in_orphan_window_pass; + + // Report clustering summary. If there are any type with non-zero clusters, + // their individual cluster number will also be printed. + VTR_LOG("----------------------------------------------------------------\n"); + VTR_LOG(" Clustering Summary \n"); + VTR_LOG("----------------------------------------------------------------\n"); + VTR_LOG("Clusters created (Self Clustering) : %zu\n", num_of_clusters_in_self_pass); + for (const auto& [block_name, count] : cluster_type_count_self_pass) { + VTR_LOG(" %-10s : %zu\n", block_name.c_str(), count); + } + VTR_LOG("Clusters created (Orphan Window Clustering) : %zu\n", num_of_clusters_in_orphan_window_pass); + for (const auto& [block_name, count] : cluster_type_count_orphan_window_pass) { + VTR_LOG(" %-10s : %zu\n", block_name.c_str(), count); + } + VTR_LOG("Total clusters : %zu\n", num_of_clusters_in_self_pass + num_of_clusters_in_orphan_window_pass); + VTR_LOG("Percent of clusters created in Orphan Window Clustering : %.2f%%\n", + 100.0f * static_cast(num_of_clusters_in_orphan_window_pass) / static_cast(num_of_clusters_in_self_pass + num_of_clusters_in_orphan_window_pass)); + + VTR_LOG("Molecules clustered in each stage breakdown : (Total of %zu)\n", total_mols_clustered); + VTR_LOG("\tSelf Clustering (%f) : %zu\n ", + static_cast(num_of_mols_clustered_in_self_pass) / static_cast(total_mols_clustered), num_of_mols_clustered_in_self_pass); + VTR_LOG("\tNeighbor Clustering (%f) : %zu\n", + static_cast(num_of_mols_clustered_in_neighbor_pass) / static_cast(total_mols_clustered), num_of_mols_clustered_in_neighbor_pass); + VTR_LOG("\tOrphan Window Clustering (%f) : %zu\n", + static_cast(num_of_mols_clustered_in_orphan_window_pass) / static_cast(total_mols_clustered), num_of_mols_clustered_in_orphan_window_pass); + VTR_LOG("----------------------------------------------------------------\n\n"); +} + +void FlatRecon::create_clusters(ClusterLegalizer& cluster_legalizer, + const PartialPlacement& p_placement) { + vtr::ScopedStartFinishTimer creating_clusters("Creating Clusters"); + + const DeviceGrid& device_grid = g_vpr_ctx.device().grid; + VTR_LOG("Device (width, height): (%zu,%zu)\n", device_grid.width(), device_grid.height()); + + // Sort the blocks according to their used external pin numbers while + // prioritizing the long carry chain molecules respectively. Then, + // group the sorted blocks by each tile. + auto tile_blocks = sort_and_group_blocks_by_tile(p_placement); + + // Initialize the tile clusters matrix to be updated in reconstruction pass + // and to be used in neighbor pass. + auto [layers, width, height] = device_grid_.dim_sizes(); + tile_clusters_matrix = vtr::NdMatrix, 3>({layers, width, height}); + + vtr::vector> + primitive_candidate_block_types = identify_primitive_candidate_block_types(); + + // Perform self clustering pass. + self_clustering(cluster_legalizer, + device_grid, + primitive_candidate_block_types, + tile_blocks); + + // Perform neighbor clustering pass. + std::unordered_set neighbor_pass_molecules = neighbor_clustering(cluster_legalizer, + primitive_candidate_block_types); + + // Perform orphan window clustering pass. + // We retry orphan-window clustering with progressively larger Manhattan radii, + // trading fewer clusters for higher displacement. Radius 8 was chosen + // empirically as a good starting point (low displacement, reasonable cluster + // count). If those clusters still don't fit the device, we retry with 16, and + // finally with the whole device. + std::vector orphan_window_search_radii = {8, 16, static_cast(device_grid.width() + device_grid.height())}; + bool fits_on_device = false; + std::unordered_set orphan_window_clusters; + for (int orphan_window_search_radius: orphan_window_search_radii) { + orphan_window_clusters = orphan_window_clustering(cluster_legalizer, + primitive_candidate_block_types, + orphan_window_search_radius); + + // Count used instances per block type. + std::map num_used_type_instances; + for (LegalizationClusterId cluster_id : cluster_legalizer.clusters()) { + if (!cluster_id.is_valid()) + continue; + t_logical_block_type_ptr cluster_type = cluster_legalizer.get_cluster_type(cluster_id); + num_used_type_instances[cluster_type]++; + } + + std::map block_type_utils; + fits_on_device = try_size_device_grid(arch_, + num_used_type_instances, + block_type_utils, + vpr_setup_.PackerOpts.target_device_utilization, + vpr_setup_.PackerOpts.device_layout); + // Exit if clusters fit on device. + if (fits_on_device) + break; + + // Destroy the orphan window clusters to recreate with bigger search radius. + VTR_LOG("Clusters did not fit on device with orphan window search radius of %d.\n", orphan_window_search_radius); + for (LegalizationClusterId cluster_id: orphan_window_clusters) { + if (!cluster_id.is_valid()) + continue; + cluster_legalizer.destroy_cluster(cluster_id); + } + orphan_window_clusters.clear(); + } + + if (!fits_on_device) { + VPR_FATAL_ERROR(VPR_ERROR_AP, "Created clusters could not fit on device."); + } + + // Report the clustering summary. + report_clustering_summary(cluster_legalizer, + neighbor_pass_molecules, + orphan_window_clusters); + + // Check and output the clustering. + cluster_legalizer.compress(); + std::unordered_set is_clock = alloc_and_load_is_clock(); + check_and_output_clustering(cluster_legalizer, vpr_setup_.PackerOpts, is_clock, &arch_); + + // Clear the data structures that uses LegalizationClusterIds + // since compress has invalidated them. + loc_to_cluster_id_placed.clear(); + cluster_locs.clear(); + tile_clusters_matrix.clear(); + + // Reset the cluster legalizer. This is required to load the packing. + cluster_legalizer.reset(); + // Regenerate the clustered netlist from the file generated previously. + // FIXME: This writing and loading from a file is wasteful. Should generate + // the clusters directly from the cluster legalizer. + vpr_load_packing(vpr_setup_, arch_); + + // Verify the packing + check_netlist(vpr_setup_.PackerOpts.pack_verbosity); + writeClusteredNetlistStats(vpr_setup_.FileNameOpts.write_block_usage); +} + +void FlatRecon::place_clusters(const PartialPlacement& p_placement) { + // Setup the global variables for placement. + g_vpr_ctx.mutable_placement().init_placement_context(vpr_setup_.PlacerOpts, arch_.directs); + g_vpr_ctx.mutable_floorplanning().update_floorplanning_context_pre_place(*g_vpr_ctx.placement().place_macros); + + // The placement will be stored in the global block loc registry. + BlkLocRegistry& blk_loc_registry = g_vpr_ctx.mutable_placement().mutable_blk_loc_registry(); + + // Create the noc cost handler used in the initial placer. + std::optional noc_cost_handler; + if (vpr_setup_.NocOpts.noc) + noc_cost_handler.emplace(blk_loc_registry.block_locs()); + + // Create the RNG container for the initial placer. + vtr::RngContainer rng(vpr_setup_.PlacerOpts.seed); + + // The partial placement has been set by the GP (if using internal VTR AP), + // or by reading in the flat placement file. Cast / copy it to the flat + // placement data structures so we can always use them. + FlatPlacementInfo flat_placement_info(atom_netlist_); + for (APBlockId ap_blk_id : ap_netlist_.blocks()) { + PackMoleculeId mol_id = ap_netlist_.block_molecule(ap_blk_id); + const t_pack_molecule& mol = prepacker_.get_molecule(mol_id); + for (AtomBlockId atom_blk_id : mol.atom_block_ids) { + if (!atom_blk_id.is_valid()) + continue; + flat_placement_info.blk_x_pos[atom_blk_id] = p_placement.block_x_locs[ap_blk_id]; + flat_placement_info.blk_y_pos[atom_blk_id] = p_placement.block_y_locs[ap_blk_id]; + flat_placement_info.blk_layer[atom_blk_id] = p_placement.block_layer_nums[ap_blk_id]; + flat_placement_info.blk_sub_tile[atom_blk_id] = p_placement.block_sub_tiles[ap_blk_id]; + } + } + + // Run the initial placer on the clusters created. + // TODO: Currently, the way initial placer sorts the blocks to place is aligned + // how self clustering passes the clusters created, so there is no need to explicitly + // prioritize these clusters. However, if it changes in time, the atoms clustered + // in neighbor pass and atoms misplaced might not match exactly. It might be safer + // to write FlatRecon's own placer in that case. + initial_placement(vpr_setup_.PlacerOpts, + vpr_setup_.PlacerOpts.constraints_file.c_str(), + vpr_setup_.NocOpts, + blk_loc_registry, + *g_vpr_ctx.placement().place_macros, + noc_cost_handler, + flat_placement_info, + rng); + + // Log some information on how good the reconstruction was. + log_flat_placement_reconstruction_info(flat_placement_info, + blk_loc_registry.block_locs(), + g_vpr_ctx.clustering().atoms_lookup, + g_vpr_ctx.atom().lookup(), + atom_netlist_, + g_vpr_ctx.clustering().clb_nlist); + + // Verify that the placement is valid for the VTR flow. + unsigned num_errors = verify_placement(blk_loc_registry, + *g_vpr_ctx.placement().place_macros, + g_vpr_ctx.clustering().clb_nlist, + g_vpr_ctx.device().grid, + g_vpr_ctx.floorplanning().cluster_constraints); + if (num_errors != 0) { + VPR_ERROR(VPR_ERROR_AP, + "\nCompleted placement consistency check, %d errors found.\n" + "Aborting program.\n", + num_errors); + } + + // Synchronize the pins in the clusters after placement. + post_place_sync(); +} + +void FlatRecon::legalize(const PartialPlacement& p_placement) { + // Start a scoped timer for the Full Legalizer stage. + vtr::ScopedStartFinishTimer full_legalizer_timer("AP Full Legalizer"); + + // The target external pin utilization is set to 1.0 to avoid over-restricting + // reconstruction due to conservative pin feasibility. The SKIP_INTRA_LB_ROUTE + // strategy speeds up reconstruction by skipping intra-LB routing checks. + std::vector target_ext_pin_util = {"1.0"}; + t_pack_high_fanout_thresholds high_fanout_thresholds(vpr_setup_.PackerOpts.high_fanout_threshold); + + ClusterLegalizer cluster_legalizer( + atom_netlist_, + prepacker_, + vpr_setup_.PackerRRGraph, + target_ext_pin_util, + high_fanout_thresholds, + ClusterLegalizationStrategy::SKIP_INTRA_LB_ROUTE, + vpr_setup_.PackerOpts.enable_pin_feasibility_filter, + arch_.models, + vpr_setup_.PackerOpts.pack_verbosity); + + // Perform clustering using partial placement. + create_clusters(cluster_legalizer, p_placement); + + // Verify that the clustering created by the full legalizer is valid. + unsigned num_clustering_errors = verify_clustering(g_vpr_ctx); + if (num_clustering_errors == 0) { + VTR_LOG("Completed clustering consistency check successfully.\n"); + } else { + VPR_ERROR(VPR_ERROR_AP, + "Completed placement consistency check, %u errors found.\n" + "Aborting program.\n", + num_clustering_errors); + } + + // Perform the initial placement on created clusters. + place_clusters(p_placement); +} + void NaiveFullLegalizer::create_clusters(const PartialPlacement& p_placement) { // PACKING: // Initialize the cluster legalizer (Packing) diff --git a/vpr/src/analytical_place/full_legalizer.h b/vpr/src/analytical_place/full_legalizer.h index 34f1f1da442..3eef240cc35 100644 --- a/vpr/src/analytical_place/full_legalizer.h +++ b/vpr/src/analytical_place/full_legalizer.h @@ -9,7 +9,9 @@ */ #include +#include #include "ap_flow_enums.h" +#include "cluster_legalizer.h" // Forward declarations class APNetlist; @@ -95,6 +97,193 @@ std::unique_ptr make_full_legalizer(e_ap_full_legalizer full_lega const t_arch& arch, const DeviceGrid& device_grid); +/** + * @brief FlatRecon: The Flat Placement Reconstruction Full Legalizer. + * + * Reconstructs (packs and places) an input flat placement with minimal + * disturbance. The flat placement may be read from a ``.fplace`` file or + * taken from Global Placement (GP). In both cases the input is expected to be + * near-legal. + * + * Before packing, molecules are sorted so that long carry chain molecules are + * priorizited. For molecules in the same priority group, the number of external pins + * is used as a tie-breaker. It then groups the molecules according to the tiles + * determined from their flat placement. + * + * The packing consists of three passes: + * 1) Self clustering: For each tile, form as few clusters as possible from + * molecules targeting that tile, and does not create more clusters than the + * tile can accommodate. Try clustering with the faster SKIP_INTRA_LB_ROUTE + * legality strategy (after each molecule is added) first; if the resulting + * cluster turns out to be unroutable, packing it is retried with the FULL + * legality checking strategy. Molecules that still cannot be clustered + * (incompatible with the tile or with the newly formed clusters) are passed + * to the neighbor pass. + * + * 2) Neighbor clustering: For each unclustered molecule, inspect clusters in + * the 8 neighboring tiles within the same layer. Tiles are processed in + * ascending order of average molecules-per-cluster. The unclustered molecule is + * added to an existing cluster if compatible (and all 8 are checked); no new + * clusters are created in this pass. + * + * 3) Orphan-window clustering: Remaining “orphan” molecules are clustered by + * repeated BFS expansions centered at seeds chosen by highest external input + * pin count. From each seed’s assigned location, try to cluster orphan molecules + * within a Manhattan distance ≤ radius. The default radius is 8 (empirically + * minimizes cluster count without inflating displacement on Titan benchmarks). + * If the resulting clusters do not fit the device, the pass is retried with + * radius 16, and finally with a radius spanning the whole device. Larger radii + * reduce cluster count but can increase displacement. + * + * After cluster creation, each cluster is placed by the initial placer at the + * grid location nearest to the centroid of its atoms. + * + * TODO: Refer to the FPT 2025 Triple-AP paper if accepted. + * + */ +class FlatRecon : public FullLegalizer { + public: + using FullLegalizer::FullLegalizer; + + /** + * @brief Perform the FlatRecon full legalization. + */ + void legalize(const PartialPlacement& p_placement) final; + + private: + /// @brief Mapping from subtile location to legalization cluster id to keep + /// track of clusters created. + /// TODO: It might make sense to store this as a 3D NDMatrix of arrays where we can + /// index into the [layer][x][y][subtile] and get the cluster ID at that location. + /// It will be faster than using an unordered map and likely more space efficient. + std::unordered_map loc_to_cluster_id_placed; + + /// @brief Mapping from a molecule id to its desired physical tile location. + vtr::vector mol_desired_physical_tile_loc; + + /// @brief Mapping from legalization cluster ids to subtile locations. Using + /// unordered_map instead of vtr::vector since LegalizationClusterIds + /// can have significant gaps as you create a new ID for each cluster + /// you attempt to create. + std::unordered_map cluster_locs; + + /// @brief 3D NDMatrix of legalization cluster ids. Stores the cluster ids at + /// that tile location and can be accessed in the format of [layer][x][y]. + /// This is stored to be used in the neighbor pass. + vtr::NdMatrix, 3> tile_clusters_matrix; + + /** + * @brief Helper method to sort and group molecules by desired tile location. + * It first sorts by being in a long carry chain, then by external input + * pin count. + * @return Mapping from tile location to sorted vector of molecules that + * want to be in that tile. + */ + std::unordered_map> + sort_and_group_blocks_by_tile(const PartialPlacement& p_placement); + + /** + * @brief Helper method to create clusters at a given tile location using + * given vector of molecules. + * + * Iterates over each subtile in the same order each time, hence trying to + * create the fewest clusters in that tile. It also checks the compatibility + * of the molecules with the tile before creating a cluster. Stores the cluster + * ids' to check their legality or clean afterwards if needed. + * + * @param tile_loc The physical tile location that clusters aimed to be created. + * @param tile_type The physical type of the tile that clusters aimed to be created. + * @param tile_molecules A vector of molecule ids aimed to be placed in that tile. + * @param cluster_legalizer The cluster legalizer which is used to create and grow clusters. + * @param primitive_candidate_block_types A list of candidate block types for the given molecule to create a cluster. + * @return The set of LegalizationClusterIds created in that tile. + */ + std::unordered_set + cluster_molecules_in_tile(const t_physical_tile_loc& tile_loc, + const t_physical_tile_type_ptr& tile_type, + const std::vector& tile_molecules, + ClusterLegalizer& cluster_legalizer, + const vtr::vector>& primitive_candidate_block_types); + + /** + * @brief Helper method to perform self clustering pass. + * + * Iterates over each tile and first tries to create the fewest clusters + * in that tile with SKIP_INTRA_LB_ROUTE strategy. If the resulting + * cluster is found to be unroutable when fully checked, retry adding the + * molecules with the FULL strategy before going to next tile. + * + * @param cluster_legalizer The cluster legalizer which is used to create and grow clusters. The result of + * this pass is an updated cluster_legalizer. + * @param device_grid The device grid used to get physical tile types. + * @param primitive_candidate_block_types A list of candidate block types for the given molecule to create a cluster. + * @param tile_blocks The list of molecules to pack in each non-empty tile. + */ + void self_clustering(ClusterLegalizer& cluster_legalizer, + const DeviceGrid& device_grid, + const vtr::vector>& primitive_candidate_block_types, + std::unordered_map>& tile_blocks); + + /** + * @brief Helper method to perform neighbor clustering. + * + * For each unclustered molecule, examines clusters in the 8 neighboring tiles. + * Neighbor tiles are processed in order of increasing average molecule density. + * The molecule is then added to an existing cluster if compatible. No new + * clusters are created in this pass. + * + * @return The set of molecule ids clustered in that pass. + */ + std::unordered_set + neighbor_clustering(ClusterLegalizer& cluster_legalizer, + const vtr::vector>& primitive_candidate_block_types); + + /** + * @brief Helper method to perform orphan window clustering. + * + * Iteratively selects a seed orphan molecule (highest external input pins). + * From the seed’s assigned location, expands within the given Manhattan + * search radius in a BFS manner to find nearby orphan molecules. Compatible + * neighbors are added to the seed’s cluster in order of proximity. After + * reaching the search radius, the process repeats with new seeds until all + * orphan molecules are clustered. + * + * @param cluster_legalizer The cluster legalizer which is used to create and grow clusters. + * @param primitive_candidate_block_types A list of candidate block types for the given molecule to create a cluster. + * @param search_radius The search radius that determines the allowed max distance from the seed + * molecule to candidate molecules. + * @return The set of LegalizationClusterIds created in that pass. + */ + std::unordered_set + orphan_window_clustering(ClusterLegalizer& cluster_legalizer, + const vtr::vector>& primitive_candidate_block_types, + int search_radius); + /** + * @brief Helper method to report the clustering summary. + */ + void report_clustering_summary(ClusterLegalizer& cluster_legalizer, + std::unordered_set& neighbor_pass_molecules, + std::unordered_set& orphan_window_clusters); + + /** + * @brief Helper method to create clusters with self, neighbor, and orphan window clustering. + * + * @param cluster_legalizer The cluster legalizer which is used to create and grow clusters. Keeps track of + * the clusters created and molecules clustered while checking cluster legality. + * @param p_placement The partial placement used to guide where each molecule should be placed. + */ + void create_clusters(ClusterLegalizer& cluster_legalizer, + const PartialPlacement& p_placement); + + /** + * @brief Helper method to perform initial placement on clusters created. + * + * Each cluster is placed by the initial placer at the grid location nearest + * to the centroid of its atoms. + */ + void place_clusters(const PartialPlacement& p_placement); +}; + /** * @brief The Naive Full Legalizer. * diff --git a/vpr/src/analytical_place/partial_placement.cpp b/vpr/src/analytical_place/partial_placement.cpp index 83fb8a5cd8d..97b0e23f779 100644 --- a/vpr/src/analytical_place/partial_placement.cpp +++ b/vpr/src/analytical_place/partial_placement.cpp @@ -102,6 +102,14 @@ bool PartialPlacement::verify_locs(const APNetlist& netlist, return false; if (netlist.block_mobility(blk_id) == APBlockMobility::FIXED) { const APFixedBlockLoc& fixed_loc = netlist.block_loc(blk_id); + if (g_vpr_ctx.atom().flat_placement_info().valid) { + // Flat placement files use the anchor positions of blocks, so to match the + // internal global placer of VTR we add 0.5 here to move the flat placement + // locations to the center of (at least 1x1) tiles. + // TODO: This should be handled more explicitly. + x_pos += 0.5f; + y_pos += 0.5f; + } if (fixed_loc.x != -1 && x_pos != fixed_loc.x) return false; if (fixed_loc.y != -1 && y_pos != fixed_loc.y) diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index 8309fe73fb8..ef88b809fcf 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -648,8 +648,8 @@ static void ShowAnalyticalPlacerOpts(const t_ap_opts& APOpts) { case e_ap_full_legalizer::APPack: VTR_LOG("appack\n"); break; - case e_ap_full_legalizer::Basic_Min_Disturbance: - VTR_LOG("basic-min-disturbance\n"); + case e_ap_full_legalizer::FlatRecon: + VTR_LOG("flat-recon\n"); break; default: VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown full_legalizer_type\n"); diff --git a/vpr/src/base/flat_placement_types.h b/vpr/src/base/flat_placement_types.h index b725751a05c..c60e40b0e61 100644 --- a/vpr/src/base/flat_placement_types.h +++ b/vpr/src/base/flat_placement_types.h @@ -70,8 +70,6 @@ class FlatPlacementInfo { static constexpr float UNDEFINED_POS = -1.f; /// @brief Identifier for an undefined sub tile. static constexpr int UNDEFINED_SUB_TILE = -1; - /// @brief Identifier for an undefined site idx. - static constexpr int UNDEFINED_SITE_IDX = -1; // The following three floating point numbers describe the flat position of // an atom block. These are floats instead of integers to allow for flat @@ -91,10 +89,6 @@ class FlatPlacementInfo { /// @brief The sub tile location of each atom block. Is UNDEFINED_SUB_TILE /// if undefined. vtr::vector blk_sub_tile; - /// @brief The flat site idx of each atom block. This is an optional index - /// into a linearized list of primitive locations within a cluster- - /// level block. Is UNDEFINED_SITE_IDX if undefined. - vtr::vector blk_site_idx; /// @brief A flag to signify if this object has been constructed with data /// or not. This makes it easier to detect if a flat placement exists @@ -135,6 +129,5 @@ class FlatPlacementInfo { , blk_y_pos(atom_netlist.blocks().size(), UNDEFINED_POS) , blk_layer(atom_netlist.blocks().size(), UNDEFINED_POS) , blk_sub_tile(atom_netlist.blocks().size(), UNDEFINED_SUB_TILE) - , blk_site_idx(atom_netlist.blocks().size(), UNDEFINED_SITE_IDX) , valid(true) {} }; diff --git a/vpr/src/base/load_flat_place.cpp b/vpr/src/base/load_flat_place.cpp index 9a413578db4..7d637df706d 100644 --- a/vpr/src/base/load_flat_place.cpp +++ b/vpr/src/base/load_flat_place.cpp @@ -14,6 +14,7 @@ #include "atom_lookup.h" #include "atom_netlist.h" #include "clustered_netlist.h" +#include "flat_placement_utils.h" #include "flat_placement_types.h" #include "globals.h" #include "vpr_context.h" @@ -39,7 +40,7 @@ static void print_flat_placement_file_header(FILE* fp) { vtr::BUILD_TIMESTAMP); fprintf(fp, "#\n"); fprintf(fp, "# This file prints the following information for each atom in the netlist:\n"); - fprintf(fp, "# # \n"); + fprintf(fp, "# # \n"); fprintf(fp, "\n"); } @@ -74,11 +75,10 @@ static void print_flat_cluster(FILE* fp, t_pb_graph_node* atom_pbgn = atom_ctx.lookup().atom_pb_bimap().atom_pb(atom)->pb_graph_node; // Print the flat placement information for this atom. - fprintf(fp, "%s %d %d %d %d %d #%zu %s\n", + fprintf(fp, "%s %d %d %d %d #%zu %s\n", atom_ctx.netlist().block_name(atom).c_str(), blk_loc.x, blk_loc.y, blk_loc.layer, blk_loc.sub_tile, - atom_pbgn->flat_site_index, static_cast(blk_id), atom_pbgn->pb_type->name); } @@ -177,10 +177,6 @@ FlatPlacementInfo read_flat_placement(const std::string& read_flat_place_file_pa // Parse the sub-tile as an integer. flat_placement_info.blk_sub_tile[atom_blk_id] = vtr::atoi(tokens[4]); - // If a site index is given, parse the site index as an integer. - if (tokens.size() >= 6 && tokens[5][0] != '#') - flat_placement_info.blk_site_idx[atom_blk_id] = vtr::atoi(tokens[5]); - // Ignore any further tokens. line_num++; @@ -263,23 +259,22 @@ void log_flat_placement_reconstruction_info( VTR_ASSERT(flat_placement_info.blk_layer[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS); VTR_ASSERT(flat_placement_info.blk_sub_tile[atom_blk_id] != FlatPlacementInfo::UNDEFINED_SUB_TILE); - // Get the (x, y, layer) position of the block. - int blk_x = flat_placement_info.blk_x_pos[atom_blk_id]; - int blk_y = flat_placement_info.blk_y_pos[atom_blk_id]; - int blk_layer = flat_placement_info.blk_layer[atom_blk_id]; + // Get the (x, y, layer) position of the block. + float blk_x = flat_placement_info.blk_x_pos[atom_blk_id]; + float blk_y = flat_placement_info.blk_y_pos[atom_blk_id]; + float blk_layer = flat_placement_info.blk_layer[atom_blk_id]; + t_flat_pl_loc blk_flat_loc({blk_x, blk_y, blk_layer}); // Get the (x, y, layer) position of the cluster that contains this block. ClusterBlockId atom_clb_id = cluster_of_atom_lookup.atom_clb(atom_blk_id); const t_block_loc& clb_loc = block_locs[atom_clb_id]; + t_physical_tile_loc tile_loc = {clb_loc.loc.x, clb_loc.loc.y, clb_loc.loc.layer}; - // Compute the distance between these two positions. - // FIXME: This will overreport large blocks. This should really be - // the distance outside of the tile you want to be placed in. - float dx = blk_x - clb_loc.loc.x; - float dy = blk_y - clb_loc.loc.y; - float dlayer = blk_layer - clb_loc.loc.layer; - // Using the Manhattan distance (L1 norm) - float dist = std::abs(dx) + std::abs(dy) + std::abs(dlayer); + // Get the L1 distance from the block location to the tile location. + // This will be the minimum distance this block needs to move. + float dist = get_manhattan_distance_to_tile(blk_flat_loc, + tile_loc, + g_vpr_ctx.device().grid); // Collect the max displacement. max_disp = std::max(max_disp, dist); @@ -309,7 +304,7 @@ void log_flat_placement_reconstruction_info( size_t num_clusters = clustered_netlist.blocks().size(); VTR_LOG("Flat Placement Reconstruction Info:\n"); VTR_LOG("\tPercent of clusters with reconstruction errors: %f\n", - static_cast(num_imperfect_clusters) / static_cast(num_clusters)); + 100.0f * static_cast(num_imperfect_clusters) / static_cast(num_clusters)); VTR_LOG("\tTotal displacement of initial placement from flat placement: %f\n", total_disp); VTR_LOG("\tAverage atom displacement of initial placement from flat placement: %f\n", @@ -317,5 +312,5 @@ void log_flat_placement_reconstruction_info( VTR_LOG("\tMax atom displacement of initial placement from flat placement: %f\n", max_disp); VTR_LOG("\tPercent of atoms misplaced from the flat placement: %f\n", - static_cast(num_atoms_missplaced) / static_cast(num_atoms)); + 100.0f * static_cast(num_atoms_missplaced) / static_cast(num_atoms)); } diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 1d1becc91d6..4164705f481 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -221,8 +221,8 @@ struct ParseAPFullLegalizer { conv_value.set_value(e_ap_full_legalizer::Naive); else if (str == "appack") conv_value.set_value(e_ap_full_legalizer::APPack); - else if (str == "basic-min-disturbance") - conv_value.set_value(e_ap_full_legalizer::Basic_Min_Disturbance); + else if (str == "flat-recon") + conv_value.set_value(e_ap_full_legalizer::FlatRecon); else { std::stringstream msg; msg << "Invalid conversion from '" << str << "' to e_ap_full_legalizer (expected one of: " << argparse::join(default_choices(), ", ") << ")"; @@ -240,8 +240,8 @@ struct ParseAPFullLegalizer { case e_ap_full_legalizer::APPack: conv_value.set_value("appack"); break; - case e_ap_full_legalizer::Basic_Min_Disturbance: - conv_value.set_value("basic-min-disturbance"); + case e_ap_full_legalizer::FlatRecon: + conv_value.set_value("flat-recon"); default: VTR_ASSERT(false); } @@ -249,7 +249,7 @@ struct ParseAPFullLegalizer { } std::vector default_choices() { - return {"naive", "appack", "basic-min-disturbance"}; + return {"naive", "appack", "flat-recon"}; } }; @@ -1847,7 +1847,12 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio file_grp.add_argument(args.write_flat_place_file, "--write_flat_place") .help( - "VPR's (or reconstructed external) placement solution in flat placement file format; this file lists cluster and intra-cluster placement coordinates for each atom and can be used to reconstruct a clustering and placement solution.") + "VPR's (or reconstructed external) placement solution in flat placement file format; this file lists (x, y, layer) coordinates and subtile for each atom and can be used to reconstruct a clustering and placement solution.") + .show_in(argparse::ShowIn::HELP_ONLY); + + file_grp.add_argument(args.write_legalized_flat_place_file, "--write_legalized_flat_place") + .help( + "VPR's (or reconstructed external) placement solution after legalization and before anneal in flat placement file format; this file lists (x, y, layer) coordinates and subtile for each atom and can be used to reconstruct a clustering and placement solution.") .show_in(argparse::ShowIn::HELP_ONLY); file_grp.add_argument(args.read_router_lookahead, "--read_router_lookahead") @@ -1957,7 +1962,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio "Controls which Full Legalizer to use in the AP Flow.\n" " * naive: Use a Naive Full Legalizer which will try to create clusters exactly where their atoms are placed.\n" " * appack: Use APPack, which takes the Packer in VPR and uses the flat atom placement to create better clusters.\n" - " * basic-min-disturbance: Use the Basic Min. Disturbance Full Legalizer which tries to reconstruct a clustered placement that is as close to the incoming flat placement as possible.") + " * flat-recon: Use the Flat Placement Reconstruction Full Legalizer which tries to reconstruct a clustered placement that is as close to the incoming flat placement as possible.") .default_value("appack") .show_in(argparse::ShowIn::HELP_ONLY); diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 2d11013569b..4bd8485dc3f 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -37,6 +37,7 @@ struct t_options { argparse::ArgValue write_constraints_file; argparse::ArgValue read_flat_place_file; argparse::ArgValue write_flat_place_file; + argparse::ArgValue write_legalized_flat_place_file; argparse::ArgValue write_placement_delay_lookup; argparse::ArgValue read_placement_delay_lookup; diff --git a/vpr/src/base/setup_vpr.cpp b/vpr/src/base/setup_vpr.cpp index 36138872419..c63222ff4bc 100644 --- a/vpr/src/base/setup_vpr.cpp +++ b/vpr/src/base/setup_vpr.cpp @@ -141,6 +141,7 @@ void SetupVPR(const t_options* options, fileNameOpts->write_constraints_file = options->write_constraints_file; fileNameOpts->read_flat_place_file = options->read_flat_place_file; fileNameOpts->write_flat_place_file = options->write_flat_place_file; + fileNameOpts->write_legalized_flat_place_file = options->write_legalized_flat_place_file; fileNameOpts->write_block_usage = options->write_block_usage; fileNameOpts->verify_file_digests = options->verify_file_digests; diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index fe08be0b365..ef989f74922 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -677,6 +677,7 @@ struct t_file_name_opts { std::string write_constraints_file; std::string read_flat_place_file; std::string write_flat_place_file; + std::string write_legalized_flat_place_file; std::string write_block_usage; bool verify_file_digests; }; diff --git a/vpr/src/pack/pack.cpp b/vpr/src/pack/pack.cpp index 7b892c24b6c..41c4912fc10 100644 --- a/vpr/src/pack/pack.cpp +++ b/vpr/src/pack/pack.cpp @@ -65,12 +65,6 @@ enum class e_packer_state { } // namespace -static bool try_size_device_grid(const t_arch& arch, - const std::map& num_type_instances, - std::map& type_util, - float target_device_utilization, - const std::string& device_layout_name); - /** * @brief The packer iteratively re-packes the netlist if it fails to find a * valid clustering. Each iteration is a state the packer is in, where @@ -634,11 +628,11 @@ std::unordered_set alloc_and_load_is_clock() { return (is_clock); } -static bool try_size_device_grid(const t_arch& arch, - const std::map& num_type_instances, - std::map& type_util, - float target_device_utilization, - const std::string& device_layout_name) { +bool try_size_device_grid(const t_arch& arch, + const std::map& num_type_instances, + std::map& type_util, + float target_device_utilization, + const std::string& device_layout_name) { auto& device_ctx = g_vpr_ctx.mutable_device(); //Build the device diff --git a/vpr/src/pack/pack.h b/vpr/src/pack/pack.h index 26b23182cb0..d4036c3196f 100644 --- a/vpr/src/pack/pack.h +++ b/vpr/src/pack/pack.h @@ -1,5 +1,7 @@ #pragma once +#include +#include #include #include @@ -12,6 +14,8 @@ struct t_ap_opts; struct t_arch; struct t_lb_type_rr_node; struct t_packer_opts; +struct t_logical_block_type; +using t_logical_block_type_ptr = const t_logical_block_type*; /** * @brief Try to pack the atom netlist into legal clusters on the given @@ -44,4 +48,27 @@ bool try_pack(const t_packer_opts& packer_opts, const PreClusterTimingManager& pre_cluster_timing_manager, const FlatPlacementInfo& flat_placement_info); +/** + * @brief Try to fit the block type instances on the given architecture. Will + * return true if successful, false otherwise. + * + * @param arch + * The architecture to try to fit the given instances. + * @param num_type_instances + * The mapping from each logical block type to the number of instances + * of the corresponding logical block type. + * @param type_util + * The utilization of each logical block type on the architecture to + * be filled. + * @param target_device_utilization + * The target device utilization. + * @param device_layout_name + * The device layout name for that architecture. + */ +bool try_size_device_grid(const t_arch& arch, + const std::map& num_type_instances, + std::map& type_util, + float target_device_utilization, + const std::string& device_layout_name); + std::unordered_set alloc_and_load_is_clock(); diff --git a/vpr/src/pack/verify_flat_placement.cpp b/vpr/src/pack/verify_flat_placement.cpp index 59bb36bbbf8..8dc7c933365 100644 --- a/vpr/src/pack/verify_flat_placement.cpp +++ b/vpr/src/pack/verify_flat_placement.cpp @@ -16,8 +16,7 @@ unsigned verify_flat_placement_for_packing(const FlatPlacementInfo& flat_placeme if (flat_placement_info.blk_x_pos.size() != atom_netlist.blocks().size() || flat_placement_info.blk_y_pos.size() != atom_netlist.blocks().size() || flat_placement_info.blk_layer.size() != atom_netlist.blocks().size() - || flat_placement_info.blk_sub_tile.size() != atom_netlist.blocks().size() - || flat_placement_info.blk_site_idx.size() != atom_netlist.blocks().size()) { + || flat_placement_info.blk_sub_tile.size() != atom_netlist.blocks().size()) { VTR_LOG_ERROR( "The number of blocks in the flat placement does not match the " "number of blocks in the atom netlist.\n"); @@ -51,12 +50,10 @@ unsigned verify_flat_placement_for_packing(const FlatPlacementInfo& flat_placeme float blk_y_pos = flat_placement_info.blk_y_pos[blk_id]; float blk_layer = flat_placement_info.blk_layer[blk_id]; int blk_sub_tile = flat_placement_info.blk_sub_tile[blk_id]; - int blk_site_idx = flat_placement_info.blk_site_idx[blk_id]; if ((blk_x_pos < 0.f && blk_x_pos != FlatPlacementInfo::UNDEFINED_POS) || (blk_y_pos < 0.f && blk_y_pos != FlatPlacementInfo::UNDEFINED_POS) || (blk_layer < 0.f && blk_layer != FlatPlacementInfo::UNDEFINED_POS) - || (blk_sub_tile < 0 && blk_sub_tile != FlatPlacementInfo::UNDEFINED_SUB_TILE) - || (blk_site_idx < 0 && blk_site_idx != FlatPlacementInfo::UNDEFINED_SITE_IDX)) { + || (blk_sub_tile < 0 && blk_sub_tile != FlatPlacementInfo::UNDEFINED_SUB_TILE)) { VTR_LOG_ERROR( "Atom block %s is placed at an invalid position on the FPGA.\n", atom_netlist.block_name(blk_id).c_str()); diff --git a/vtr_flow/parse/parse_config/vpr_ap_reconstruction.txt b/vtr_flow/parse/parse_config/vpr_ap_reconstruction.txt new file mode 100644 index 00000000000..a08db936442 --- /dev/null +++ b/vtr_flow/parse/parse_config/vpr_ap_reconstruction.txt @@ -0,0 +1,8 @@ +%include "vpr_standard.txt" + +post_fl_atom_err;vpr.out;\s*Percent of atoms misplaced from the flat placement: (.*) +post_fl_total_disp;vpr.out;\s*Total displacement of initial placement from flat placement: (.*) +post_fl_avg_disp;vpr.out;\s*Average atom displacement of initial placement from flat placement: (.*) +post_fl_max_disp;vpr.out;\s*Max atom displacement of initial placement from flat placement: (.*) +ap_fl_max_rss;vpr.out;AP Full Legalizer took .*max_rss (.*?) MiB +num_total_clusters;vpr.out;^\s*Total\s+clusters\s*:\s*(\d+) diff --git a/vtr_flow/parse/pass_requirements/pass_requirements_ap_reconstruction.txt b/vtr_flow/parse/pass_requirements/pass_requirements_ap_reconstruction.txt new file mode 100644 index 00000000000..46bb1a4f0ef --- /dev/null +++ b/vtr_flow/parse/pass_requirements/pass_requirements_ap_reconstruction.txt @@ -0,0 +1,7 @@ +%include "common/pass_requirements.vpr_status.txt" + +post_fl_atom_err;Range(0.7,1.30) +post_fl_total_disp;Range(0.7,1.30) +num_total_clusters;Range(0.9,1.10) +ap_fl_max_rss;Range(0.8,1.20) + diff --git a/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt b/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt index 6331b8d94e4..d516047a128 100644 --- a/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt +++ b/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt @@ -31,4 +31,4 @@ total_runtime;vpr.out;The entire flow of VPR took (.*) seconds num_clb;vpr.out;Netlist clb blocks:\s*(\d+) num_lab;vpr.out;Netlist LAB blocks:\s*(\d+) -num_pre_packed_blocks;vpr.out;\s+total blocks:\s*(\d+),.* +num_pre_packed_blocks;vpr.out;\s+total blocks:\s*(\d+),.* \ No newline at end of file diff --git a/vtr_flow/parse/qor_config/qor_ap_flatrecon_fl_fixed_chan_width.txt b/vtr_flow/parse/qor_config/qor_ap_flatrecon_fl_fixed_chan_width.txt new file mode 100644 index 00000000000..de2a6ccc287 --- /dev/null +++ b/vtr_flow/parse/qor_config/qor_ap_flatrecon_fl_fixed_chan_width.txt @@ -0,0 +1,11 @@ +# This collects QoR data that is interesting for the Flat Placement +# Reconstruction - flatrecon on a fixed channel width. + +vpr_status;output.txt;vpr_status=(.*) +post_fl_atom_err;vpr.out;\s*Percent of atoms misplaced from the flat placement: (.*) +post_fl_total_disp;vpr.out;\s*Total displacement of initial placement from flat placement: (.*) +post_fl_avg_disp;vpr.out;\s*Average atom displacement of initial placement from flat placement: (.*) +post_fl_max_disp;vpr.out;\s*Max atom displacement of initial placement from flat placement: (.*) +ap_fl_max_rss;vpr.out;AP Full Legalizer took .*max_rss (.*?) MiB +num_total_clusters;vpr.out;^\s*Total\s+clusters\s*:\s*(\d+) + diff --git a/vtr_flow/scripts/get_flat_placement_files.py b/vtr_flow/scripts/get_flat_placement_files.py new file mode 100755 index 00000000000..7220958c2c2 --- /dev/null +++ b/vtr_flow/scripts/get_flat_placement_files.py @@ -0,0 +1,68 @@ +#!/usr/bin/env python3 +""" + Script to get the Flat Placement Files. +""" + +import sys +import os +import argparse +import subprocess +import textwrap + + +def parse_args(): + """ + Parses and returns script's arguments + """ + + description = textwrap.dedent( + """ + Extracts the flat placemnets for the Titan benchmarks which are + stored in zip format to reduce the amount of space they take up. + """ + ) + parser = argparse.ArgumentParser( + formatter_class=argparse.ArgumentDefaultsHelpFormatter, description=description + ) + + parser.add_argument( + "--vtr_flow_dir", + required=True, + help="The 'vtr_flow' directory under the VTR tree.", + ) + + return parser.parse_args() + + +def main(): + """ + Main function + """ + + args = parse_args() + + # A list of the zipped flat placements to uncompress. + flat_placement_files = [ + f"{args.vtr_flow_dir}/tasks/regression_tests/" + "vtr_reg_nightly_test7/ap_reconstruction/constraints/flat_placements.zip", + ] + + # For each zipped flat placement, unzip it into its directory. + for flat_placement_file in flat_placement_files: + # Check that the file exists. + if not os.path.exists(flat_placement_file): + print(f"Error: Unable to find zipped flat placement: {flat_placement_file}") + sys.exit(1) + + # Unzip it. + print(f"Unzipping Flat Placement File: {flat_placement_file}") + subprocess.call( + f"unzip {flat_placement_file} -d {os.path.dirname(flat_placement_file)}", + shell=True, + ) + + sys.exit(0) + + +if __name__ == "__main__": + main() diff --git a/vtr_flow/scripts/python_libs/vtr/task.py b/vtr_flow/scripts/python_libs/vtr/task.py index 3d063d05202..0f0b638a102 100644 --- a/vtr_flow/scripts/python_libs/vtr/task.py +++ b/vtr_flow/scripts/python_libs/vtr/task.py @@ -327,6 +327,7 @@ def parse_circuit_constraint_list(circuit_constraint_list, circuits_list, arch_l "device", "constraints", "route_chan_width", + "read_flat_place", ] ) @@ -797,6 +798,10 @@ def apply_cmd_line_circuit_constraints(cmd, circuit, config): constrained_route_w = config.circuit_constraints[circuit]["route_chan_width"] if constrained_route_w is not None: cmd += ["--route_chan_width", constrained_route_w] + # Check if the circuit has a flat placement to read. + flat_placement_file = config.circuit_constraints[circuit]["read_flat_place"] + if flat_placement_file is not None: + cmd += ["--read_flat_place", flat_placement_file] def resolve_vtr_source_file(config, filename, base_dir=""): diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/config/config.txt new file mode 100644 index 00000000000..c6a3db15e15 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/config/config.txt @@ -0,0 +1,38 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/constraints + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=spree.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(spree.blif, device=vtr_extra_small) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(spree.blif, route_chan_width=78) + +# Reaf flat placement constraints +circuit_constraint_list_add=(spree.blif, read_flat_place=../../../../../basic_flat_recon/constraints/spree.fplace) + +# Parse info and how to parse +parse_file=vpr_ap_reconstruction.txt + +# How to parse QoR info +qor_parse_file=qor_ap_flatrecon_fl_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_reconstruction.txt + +# Pass the script params while writing the vpr constraints. +# Starting from vpr since we want to test on the same blif file. The flat placement file will share same atom names here. +script_params=-track_memory_usage --timing_analysis off --analytical_place --ap_detailed_placer none --ap_full_legalizer flat-recon -starting_stage vpr diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/config/golden_results.txt new file mode 100644 index 00000000000..5956a77cba0 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time post_fl_atom_err post_fl_total_disp post_fl_avg_disp post_fl_max_disp ap_fl_max_rss num_total_clusters +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.blif common 1.09 vpr 84.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 61 45 3 1 success v8.0.0-13835-g615520f537 Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-65-generic x86_64 2025-08-27T08:45:05 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing/vtr_flow/tasks 86636 45 32 944 0 1 800 142 20 20 400 -1 vtr_extra_small -1 -1 -1 -1 -1 -1 -1 -1 84.6 MiB 0.72 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84.6 MiB 0.72 84.6 MiB 0.71 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.000000 0.000000 0.000000 0.000000 84.6 142 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/constraints/spree.blif b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/constraints/spree.blif new file mode 100644 index 00000000000..cdc3b2a7f6e --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/constraints/spree.blif @@ -0,0 +1,6178 @@ +# Benchmark "system" written by ABC on Wed Aug 27 09:20:54 2025 + + +.model system + + +.inputs boot_idata~19 boot_idata~16 boot_iaddr~0 boot_iaddr~1 clk resetn boot_daddr~5 boot_daddr~6 boot_iaddr~19 boot_daddr~7 \ + boot_iaddr~15 boot_ddata~2 boot_daddr~8 boot_daddr~9 boot_daddr~10 boot_daddr~11 boot_daddr~12 boot_daddr~18 boot_iaddr~17 \ + boot_daddr~22 boot_daddr~23 boot_daddr~1 boot_daddr~26 boot_daddr~2 boot_daddr~27 boot_iaddr~18 boot_iaddr~12 boot_ddata~0 \ + boot_daddr~3 boot_ddata~1 boot_idata~12 boot_daddr~4 boot_iwe boot_idata~31 boot_idata~30 boot_idata~29 boot_iaddr~8 \ + boot_idata~28 boot_iaddr~14 boot_idata~11 boot_idata~27 boot_idata~26 boot_iaddr~7 boot_iaddr~6 boot_idata~25 boot_iaddr~9 \ + boot_idata~10 boot_iaddr~11 boot_daddr~17 boot_iaddr~2 boot_daddr~15 boot_daddr~16 boot_daddr~20 boot_daddr~19 boot_idata~24 \ + boot_iaddr~16 boot_iaddr~13 boot_daddr~31 boot_daddr~13 boot_daddr~14 boot_iaddr~10 boot_ddata~3 boot_ddata~13 boot_daddr~0 \ + boot_daddr~21 boot_ddata~8 boot_ddata~10 boot_ddata~9 boot_idata~17 boot_ddata~4 boot_ddata~5 boot_ddata~6 boot_ddata~7 \ + boot_daddr~30 boot_daddr~28 boot_daddr~29 boot_idata~23 boot_idata~22 boot_idata~21 boot_iaddr~5 boot_iaddr~4 boot_ddata~12 \ + boot_ddata~11 boot_idata~13 boot_daddr~25 boot_daddr~24 boot_idata~20 boot_iaddr~3 boot_idata~18 boot_ddata~14 boot_iaddr~20 \ + boot_iaddr~21 boot_ddata~15 boot_ddata~16 boot_ddata~17 boot_ddata~18 boot_ddata~19 boot_ddata~20 boot_ddata~21 boot_ddata~22 \ + boot_ddata~23 boot_ddata~24 boot_ddata~25 boot_ddata~26 boot_ddata~27 boot_ddata~28 boot_ddata~29 boot_ddata~30 boot_ddata~31 \ + boot_dwe boot_idata~14 boot_iaddr~22 boot_iaddr~23 boot_iaddr~24 boot_iaddr~25 boot_iaddr~26 boot_iaddr~27 boot_idata~15 \ + boot_iaddr~28 boot_iaddr~29 boot_iaddr~30 boot_iaddr~31 boot_idata~0 boot_idata~1 boot_idata~2 boot_idata~3 boot_idata~4 \ + boot_idata~5 boot_idata~6 boot_idata~7 boot_idata~8 boot_idata~9 + + +.outputs nop7_q~31 nop7_q~30 nop7_q~21 nop7_q~20 nop7_q~29 nop7_q~19 nop7_q~18 nop7_q~28 nop7_q~17 nop7_q~16 nop7_q~27 \ + nop7_q~15 nop7_q~26 nop7_q~14 nop7_q~25 nop7_q~13 nop7_q~12 nop7_q~24 nop7_q~11 nop7_q~23 nop7_q~10 nop7_q~9 nop7_q~22 \ + nop7_q~8 nop7_q~7 nop7_q~6 nop7_q~0 nop7_q~1 nop7_q~2 nop7_q~3 nop7_q~4 nop7_q~5 + + + +.latch n654 $sdffe~489^Q~0 re clk 0 + + +.latch n659 $sdffe~488^Q~0 re clk 0 + + +.latch n664 $dffe~10^Q~0 re clk 0 + + +.latch n669 $dff~84^Q~1 re clk 0 + + +.latch n674 $dff~84^Q~2 re clk 0 + + +.latch n679 $dff~84^Q~3 re clk 0 + + +.latch n684 $dff~84^Q~4 re clk 0 + + +.latch n689 $dff~84^Q~5 re clk 0 + + +.latch n694 $dff~84^Q~6 re clk 0 + + +.latch n699 $sdff~432^Q~0 re clk 0 + + +.latch n704 $dffe~3^Q~0 re clk 0 + + +.latch li011 lo011 re clk 0 + + +.latch n714 $sdffe~483^Q~20 re clk 0 + + +.latch n719 $sdffe~483^Q~21 re clk 0 + + +.latch n724 $sdffe~483^Q~22 re clk 0 + + +.latch n729 $sdffe~483^Q~23 re clk 0 + + +.latch n734 $sdffe~483^Q~24 re clk 0 + + +.latch n739 $sdffe~483^Q~25 re clk 0 + + +.latch n744 $auto$simplemap.cc:248:simplemap_eqne$3403[0] re clk 0 + + +.latch n749 $auto$simplemap.cc:248:simplemap_eqne$4611[1] re clk 0 + + +.latch n754 $dffe~8^Q~0 re clk 0 + + +.latch n759 $auto$simplemap.cc:248:simplemap_eqne$3524[1] re clk 0 + + +.latch n764 $dffe~8^Q~3 re clk 0 + + +.latch li023 lo023 re clk 0 + + +.latch li024 lo024 re clk 0 + + +.latch li025 lo025 re clk 0 + + +.latch li026 lo026 re clk 0 + + +.latch li027 lo027 re clk 0 + + +.latch n794 $dff~499^Q~0 re clk 0 + + +.latch n799 $sdff~479^Q~0 re clk 0 + + +.latch n804 $dff~82^Q~0 re clk 0 + + +.latch n809 $dff~82^Q~1 re clk 0 + + +.latch n814 $dff~80^Q~1 re clk 0 + + +.latch n819 $dff~80^Q~2 re clk 0 + + +.latch n824 $dffe~7^Q~0 re clk 0 + + +.latch n829 $dff~83^Q~1 re clk 0 + + +.latch n834 $dff~83^Q~2 re clk 0 + + +.latch n839 $dff~83^Q~3 re clk 0 + + +.latch n844 $dff~83^Q~4 re clk 0 + + +.latch n849 $dff~83^Q~5 re clk 0 + + +.latch n854 $dffe~6^Q~0 re clk 0 + + +.latch n859 $auto$rtlil.cc:3155:NotGate$9410 re clk 0 + + +.latch n864 $sdffe~483^Q~17 re clk 0 + + +.latch n869 $sdffe~483^Q~18 re clk 0 + + +.latch n874 $sdffe~483^Q~19 re clk 0 + + +.latch n879 $dff~79^Q~1 re clk 0 + + +.latch n884 $dff~79^Q~2 re clk 0 + + +.latch n889 $dffe~9^Q~0 re clk 0 + + +.latch n894 $dff~81^Q~0 re clk 0 + + +.latch n899 $dff~81^Q~1 re clk 0 + + +.latch n904 $dffe~4^Q~0 re clk 0 + + +.latch li051 lo051 re clk 0 + + +.latch li052 lo052 re clk 0 + + +.latch li053 lo053 re clk 0 + + +.latch li054 lo054 re clk 0 + + +.latch li055 lo055 re clk 0 + + +.latch li056 lo056 re clk 0 + + +.latch li057 lo057 re clk 0 + + +.latch li058 lo058 re clk 0 + + +.latch li059 lo059 re clk 0 + + +.latch li060 lo060 re clk 0 + + +.latch li061 lo061 re clk 0 + + +.latch li062 lo062 re clk 0 + + +.latch li063 lo063 re clk 0 + + +.latch li064 lo064 re clk 0 + + +.latch li065 lo065 re clk 0 + + +.latch li066 lo066 re clk 0 + + +.latch li067 lo067 re clk 0 + + +.latch li068 lo068 re clk 0 + + +.latch li069 lo069 re clk 0 + + +.latch li070 lo070 re clk 0 + + +.latch li071 lo071 re clk 0 + + +.latch li072 lo072 re clk 0 + + +.latch li073 lo073 re clk 0 + + +.latch li074 lo074 re clk 0 + + +.latch li075 lo075 re clk 0 + + +.latch li076 lo076 re clk 0 + + +.latch li077 lo077 re clk 0 + + +.latch li078 lo078 re clk 0 + + +.latch li079 lo079 re clk 0 + + +.latch li080 lo080 re clk 0 + + +.latch li081 lo081 re clk 0 + + +.latch li082 lo082 re clk 0 + + +.latch li083 lo083 re clk 0 + + +.latch li084 lo084 re clk 0 + + +.latch li085 lo085 re clk 0 + + +.latch li086 lo086 re clk 0 + + +.latch li087 lo087 re clk 0 + + +.latch li088 lo088 re clk 0 + + +.latch li089 lo089 re clk 0 + + +.latch li090 lo090 re clk 0 + + +.latch li091 lo091 re clk 0 + + +.latch li092 lo092 re clk 0 + + +.latch li093 lo093 re clk 0 + + +.latch li094 lo094 re clk 0 + + +.latch li095 lo095 re clk 0 + + +.latch li096 lo096 re clk 0 + + +.latch li097 lo097 re clk 0 + + +.latch li098 lo098 re clk 0 + + +.latch li099 lo099 re clk 0 + + +.latch li100 lo100 re clk 0 + + +.latch li101 lo101 re clk 0 + + +.latch li102 lo102 re clk 0 + + +.latch li103 lo103 re clk 0 + + +.latch li104 lo104 re clk 0 + + +.latch li105 lo105 re clk 0 + + +.latch li106 lo106 re clk 0 + + +.latch li107 lo107 re clk 0 + + +.latch li108 lo108 re clk 0 + + +.latch li109 lo109 re clk 0 + + +.latch li110 lo110 re clk 0 + + +.latch n1209 $sdff~476^Q~0 re clk 0 + + +.latch n1214 $sdff~476^Q~1 re clk 0 + + +.latch n1219 $sdff~476^Q~2 re clk 0 + + +.latch n1224 $sdff~476^Q~3 re clk 0 + + +.latch n1229 $sdff~476^Q~4 re clk 0 + + +.latch n1234 $sdff~476^Q~5 re clk 0 + + +.latch n1239 $sdff~476^Q~6 re clk 0 + + +.latch n1244 $sdff~476^Q~7 re clk 0 + + +.latch n1249 $sdff~476^Q~8 re clk 0 + + +.latch n1254 $sdff~476^Q~9 re clk 0 + + +.latch n1259 $sdff~476^Q~10 re clk 0 + + +.latch n1264 $sdff~476^Q~11 re clk 0 + + +.latch n1269 $sdff~476^Q~12 re clk 0 + + +.latch n1274 $sdff~476^Q~13 re clk 0 + + +.latch n1279 $sdff~476^Q~14 re clk 0 + + +.latch n1284 $sdff~476^Q~15 re clk 0 + + +.latch n1289 $sdffe~487^Q~0 re clk 0 + + +.latch n1294 $sdffe~487^Q~1 re clk 0 + + +.latch n1299 $sdffe~487^Q~2 re clk 0 + + +.latch n1304 $sdffe~487^Q~3 re clk 0 + + +.latch n1309 $sdffe~487^Q~4 re clk 0 + + +.latch n1314 $sdffe~487^Q~5 re clk 0 + + +.latch n1319 $sdffe~487^Q~6 re clk 0 + + +.latch n1324 $sdffe~487^Q~7 re clk 0 + + +.latch n1329 $sdffe~487^Q~8 re clk 0 + + +.latch n1334 $sdffe~487^Q~9 re clk 0 + + +.latch n1339 $sdffe~487^Q~10 re clk 0 + + +.latch n1344 $sdffe~487^Q~11 re clk 0 + + +.latch n1349 $sdffe~487^Q~12 re clk 0 + + +.latch n1354 $sdffe~487^Q~13 re clk 0 + + +.latch n1359 $sdffe~487^Q~14 re clk 0 + + +.latch n1364 $sdffe~487^Q~15 re clk 0 + + +.latch n1369 $sdffe~487^Q~16 re clk 0 + + +.latch n1374 $sdffe~487^Q~17 re clk 0 + + +.latch n1379 $sdffe~487^Q~18 re clk 0 + + +.latch n1384 $sdffe~487^Q~19 re clk 0 + + +.latch n1389 $sdffe~487^Q~20 re clk 0 + + +.latch n1394 $sdffe~487^Q~21 re clk 0 + + +.latch n1399 $sdffe~487^Q~22 re clk 0 + + +.latch n1404 $sdffe~487^Q~23 re clk 0 + + +.latch n1409 $sdffe~487^Q~24 re clk 0 + + +.latch n1414 $sdffe~487^Q~25 re clk 0 + + +.latch n1419 $sdffe~487^Q~26 re clk 0 + + +.latch n1424 $sdffe~487^Q~27 re clk 0 + + +.latch n1429 $sdffe~487^Q~28 re clk 0 + + +.latch n1434 $sdffe~487^Q~29 re clk 0 + + +.latch n1439 $sdffe~487^Q~30 re clk 0 + + +.latch n1444 $sdffe~487^Q~31 re clk 0 + + +.latch n1449 $sdffe~12^Q~0 re clk 0 + + +.latch n1454 $sdffe~12^Q~1 re clk 0 + + +.latch n1459 $sdffe~12^Q~2 re clk 0 + + +.latch n1464 $sdffe~12^Q~3 re clk 0 + + +.latch n1469 $sdffe~12^Q~4 re clk 0 + + +.latch n1474 $sdffe~12^Q~5 re clk 0 + + +.latch n1479 $sdffe~12^Q~6 re clk 0 + + +.latch n1484 $sdffe~12^Q~7 re clk 0 + + +.latch n1489 $sdffe~13^Q~0 re clk 0 + + +.latch n1494 $sdffe~13^Q~1 re clk 0 + + +.latch n1499 $sdffe~13^Q~2 re clk 0 + + +.latch n1504 $sdffe~13^Q~3 re clk 0 + + +.latch n1509 $sdffe~13^Q~4 re clk 0 + + +.latch n1514 $sdffe~13^Q~5 re clk 0 + + +.latch n1519 $sdffe~13^Q~6 re clk 0 + + +.latch n1524 $sdffe~13^Q~7 re clk 0 + + +.latch li175 lo175 re clk 0 + + +.latch li176 lo176 re clk 0 + + +.latch li177 lo177 re clk 0 + + +.latch li178 lo178 re clk 0 + + +.latch li179 lo179 re clk 0 + + +.latch li180 lo180 re clk 0 + + +.latch li181 lo181 re clk 0 + + +.latch li182 lo182 re clk 0 + + +.latch li183 lo183 re clk 0 + + +.latch li184 lo184 re clk 0 + + +.latch li185 lo185 re clk 0 + + +.latch li186 lo186 re clk 0 + + +.latch li187 lo187 re clk 0 + + +.latch li188 lo188 re clk 0 + + +.latch li189 lo189 re clk 0 + + +.latch n1604 $dffe~2^Q~0 re clk 0 + + +.latch n1609 $sdffe~460^Q~0 re clk 0 + + +.latch n1614 $dffe~1^Q~0 re clk 0 + + +.latch n1619 $sdffce~11^Q~0 re clk 0 + + +.latch n1629 $auto$simplemap.cc:248:simplemap_eqne$4422[0] re clk 0 + + +.latch n1634 $auto$simplemap.cc:248:simplemap_eqne$4492[1] re clk 0 + + +.latch n1639 $auto$simplemap.cc:248:simplemap_eqne$4422[2] re clk 0 + + +.latch n1644 $auto$simplemap.cc:248:simplemap_eqne$4422[3] re clk 0 + + +.latch n1649 $auto$simplemap.cc:248:simplemap_eqne$4422[4] re clk 0 + + +.latch n1654 $auto$simplemap.cc:248:simplemap_eqne$4422[5] re clk 0 + + + + +.subckt adder cin=$add~482^ADD~4-0[0] b=$auto$simplemap.cc:248:simplemap_eqne$4218[0] a=$sdffe~15^Q~0 \ + sumout=$add~482^ADD~4-1[1] cout=$add~482^ADD~4-1[0] + + +.subckt adder cin=$add~482^ADD~4-1[0] b=$auto$simplemap.cc:248:simplemap_eqne$4287[1] a=$sdffe~15^Q~1 \ + sumout=$add~482^ADD~4-2[1] cout=$add~482^ADD~4-2[0] + + +.subckt adder cin=$add~482^ADD~4-2[0] b=$auto$simplemap.cc:248:simplemap_eqne$3720[2] a=$sdffe~15^Q~2 \ + sumout=$add~482^ADD~4-3[1] cout=$add~482^ADD~4-3[0] + + +.subckt adder cin=$add~482^ADD~4-3[0] b=$auto$simplemap.cc:248:simplemap_eqne$3720[3] a=$sdffe~15^Q~3 \ + sumout=$add~482^ADD~4-4[1] cout=$add~482^ADD~4-4[0] + + +.subckt adder cin=$add~482^ADD~4-4[0] b=$auto$simplemap.cc:248:simplemap_eqne$3720[4] a=$sdffe~15^Q~4 \ + sumout=$add~482^ADD~4-5[1] cout=$add~482^ADD~4-5[0] + + +.subckt adder cin=$add~482^ADD~4-5[0] b=$auto$simplemap.cc:248:simplemap_eqne$4589[5] a=$sdffe~15^Q~5 \ + sumout=$add~482^ADD~4-6[1] cout=$add~482^ADD~4-6[0] + + +.subckt adder cin=$add~482^ADD~4-6[0] b=$sdffe~14^Q~6 a=$sdffe~15^Q~6 sumout=$add~482^ADD~4-7[1] cout=$add~482^ADD~4-7[0] + + +.subckt adder cin=$add~482^ADD~4-7[0] b=$sdffe~14^Q~7 a=$sdffe~15^Q~7 sumout=$add~482^ADD~4-8[1] cout=$add~482^ADD~4-8[0] + + +.subckt adder cin=$add~482^ADD~4-8[0] b=$sdffe~14^Q~8 a=$sdffe~15^Q~8 sumout=$add~482^ADD~4-9[1] cout=$add~482^ADD~4-9[0] + + +.subckt adder cin=$add~482^ADD~4-9[0] b=$sdffe~14^Q~9 a=$sdffe~15^Q~9 sumout=$add~482^ADD~4-10[1] cout=$add~482^ADD~4-10[0] + + +.subckt adder cin=$add~482^ADD~4-10[0] b=$sdffe~14^Q~10 a=$sdffe~15^Q~10 sumout=$add~482^ADD~4-11[1] \ + cout=$add~482^ADD~4-11[0] + + +.subckt adder cin=$add~482^ADD~4-11[0] b=$sdffe~14^Q~11 a=$sdffe~15^Q~11 sumout=$add~482^ADD~4-12[1] \ + cout=$add~482^ADD~4-12[0] + + +.subckt adder cin=$add~482^ADD~4-12[0] b=$sdffe~14^Q~12 a=$sdffe~15^Q~12 sumout=$add~482^ADD~4-13[1] \ + cout=$add~482^ADD~4-13[0] + + +.subckt adder cin=$add~482^ADD~4-13[0] b=$sdffe~14^Q~13 a=$sdffe~15^Q~13 sumout=$add~482^ADD~4-14[1] \ + cout=$add~482^ADD~4-14[0] + + +.subckt adder cin=$add~482^ADD~4-14[0] b=$sdffe~14^Q~14 a=$sdffe~15^Q~14 sumout=$add~482^ADD~4-15[1] \ + cout=$add~482^ADD~4-15[0] + + +.subckt adder cin=$add~482^ADD~4-15[0] b=$sdffe~14^Q~15 a=$sdffe~15^Q~15 sumout=$add~482^ADD~4-16[1] \ + cout=$add~482^ADD~4-16[0] + + +.subckt adder cin=$add~482^ADD~4-16[0] b=gnd a=$sdffe~15^Q~16 sumout=$add~482^ADD~4-17[1] cout=$add~482^ADD~4-17[0] + + +.subckt adder cin=$add~482^ADD~4-17[0] b=gnd a=$sdffe~15^Q~17 sumout=$add~482^ADD~4-18[1] cout=$add~482^ADD~4-18[0] + + +.subckt adder cin=$add~482^ADD~4-18[0] b=gnd a=$sdffe~15^Q~18 sumout=$add~482^ADD~4-19[1] cout=$add~482^ADD~4-19[0] + + +.subckt adder cin=$add~482^ADD~4-19[0] b=gnd a=$sdffe~15^Q~19 sumout=$add~482^ADD~4-20[1] cout=$add~482^ADD~4-20[0] + + +.subckt adder cin=$add~482^ADD~4-20[0] b=gnd a=$sdffe~15^Q~20 sumout=$add~482^ADD~4-21[1] cout=$add~482^ADD~4-21[0] + + +.subckt adder cin=$add~482^ADD~4-21[0] b=gnd a=$sdffe~15^Q~21 sumout=$add~482^ADD~4-22[1] cout=$add~482^ADD~4-22[0] + + +.subckt adder cin=$add~482^ADD~4-22[0] b=gnd a=$sdffe~15^Q~22 sumout=$add~482^ADD~4-23[1] cout=$add~482^ADD~4-23[0] + + +.subckt adder cin=$add~482^ADD~4-23[0] b=gnd a=$sdffe~15^Q~23 sumout=$add~482^ADD~4-24[1] cout=$add~482^ADD~4-24[0] + + +.subckt adder cin=$add~482^ADD~4-24[0] b=gnd a=$sdffe~15^Q~24 sumout=$add~482^ADD~4-25[1] cout=$add~482^ADD~4-25[0] + + +.subckt adder cin=$add~482^ADD~4-25[0] b=gnd a=$sdffe~15^Q~25 sumout=$add~482^ADD~4-26[1] cout=$add~482^ADD~4-26[0] + + +.subckt adder cin=$add~482^ADD~4-26[0] b=gnd a=$sdffe~15^Q~26 sumout=$add~482^ADD~4-27[1] cout=$add~482^ADD~4-27[0] + + +.subckt adder cin=$add~482^ADD~4-27[0] b=gnd a=$sdffe~15^Q~27 sumout=$add~482^ADD~4-28[1] cout=$add~482^ADD~4-28[0] + + +.subckt adder cin=$add~482^ADD~4-28[0] b=gnd a=$sdffe~15^Q~28 sumout=$add~482^ADD~4-29[1] cout=$add~482^ADD~4-29[0] + + +.subckt adder cin=$add~482^ADD~4-29[0] b=gnd a=$sdffe~15^Q~29 sumout=$add~482^ADD~4-30[1] cout=$add~482^ADD~4-30[0] + + +.subckt adder cin=$add~446^ADD~5-0[0] b=vcc a=$dffe~447^Q~0 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[30] \ + cout=$add~446^ADD~5-1[0] + + +.subckt adder cin=$add~446^ADD~5-1[0] b=unconn a=$dffe~447^Q~1 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[31] \ + cout=$add~446^ADD~5-2[0] + + +.subckt adder cin=$add~446^ADD~5-2[0] b=unconn a=$dffe~447^Q~2 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[32] \ + cout=$add~446^ADD~5-3[0] + + +.subckt adder cin=$add~446^ADD~5-3[0] b=unconn a=$dffe~447^Q~3 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[33] \ + cout=$add~446^ADD~5-4[0] + + +.subckt adder cin=$add~446^ADD~5-4[0] b=unconn a=$dffe~447^Q~4 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[34] \ + cout=$add~446^ADD~5-5[0] + + +.subckt adder cin=$add~446^ADD~5-5[0] b=unconn a=$dffe~447^Q~5 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[35] \ + cout=$add~446^ADD~5-6[0] + + +.subckt adder cin=$add~446^ADD~5-6[0] b=unconn a=$dffe~447^Q~6 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[36] \ + cout=$add~446^ADD~5-7[0] + + +.subckt adder cin=$add~446^ADD~5-7[0] b=unconn a=$dffe~447^Q~7 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[37] \ + cout=$add~446^ADD~5-8[0] + + +.subckt adder cin=$add~446^ADD~5-8[0] b=unconn a=$dffe~447^Q~8 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[38] \ + cout=$add~446^ADD~5-9[0] + + +.subckt adder cin=$add~446^ADD~5-9[0] b=unconn a=$dffe~447^Q~9 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[39] \ + cout=$add~446^ADD~5-10[0] + + +.subckt adder cin=$add~446^ADD~5-10[0] b=unconn a=$dffe~447^Q~10 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[40] \ + cout=$add~446^ADD~5-11[0] + + +.subckt adder cin=$add~446^ADD~5-11[0] b=unconn a=$dffe~447^Q~11 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[41] \ + cout=$add~446^ADD~5-12[0] + + +.subckt adder cin=$add~446^ADD~5-12[0] b=unconn a=$dffe~447^Q~12 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[42] \ + cout=$add~446^ADD~5-13[0] + + +.subckt adder cin=$add~446^ADD~5-13[0] b=unconn a=$dffe~447^Q~13 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[43] \ + cout=$add~446^ADD~5-14[0] + + +.subckt adder cin=$add~446^ADD~5-14[0] b=unconn a=$dffe~447^Q~14 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[44] \ + cout=$add~446^ADD~5-15[0] + + +.subckt adder cin=$add~446^ADD~5-15[0] b=unconn a=$dffe~447^Q~15 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[45] \ + cout=$add~446^ADD~5-16[0] + + +.subckt adder cin=$add~446^ADD~5-16[0] b=unconn a=$dffe~447^Q~16 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[46] \ + cout=$add~446^ADD~5-17[0] + + +.subckt adder cin=$add~446^ADD~5-17[0] b=unconn a=$dffe~447^Q~17 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[47] \ + cout=$add~446^ADD~5-18[0] + + +.subckt adder cin=$add~446^ADD~5-18[0] b=unconn a=$dffe~447^Q~18 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[48] \ + cout=$add~446^ADD~5-19[0] + + +.subckt adder cin=$add~446^ADD~5-19[0] b=unconn a=$dffe~447^Q~19 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[49] \ + cout=$add~446^ADD~5-20[0] + + +.subckt adder cin=$add~446^ADD~5-20[0] b=unconn a=$dffe~447^Q~20 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[50] \ + cout=$add~446^ADD~5-21[0] + + +.subckt adder cin=$add~446^ADD~5-21[0] b=unconn a=$dffe~447^Q~21 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[51] \ + cout=$add~446^ADD~5-22[0] + + +.subckt adder cin=$add~446^ADD~5-22[0] b=unconn a=$dffe~447^Q~22 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[52] \ + cout=$add~446^ADD~5-23[0] + + +.subckt adder cin=$add~446^ADD~5-23[0] b=unconn a=$dffe~447^Q~23 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[53] \ + cout=$add~446^ADD~5-24[0] + + +.subckt adder cin=$add~446^ADD~5-24[0] b=unconn a=$dffe~447^Q~24 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[54] \ + cout=$add~446^ADD~5-25[0] + + +.subckt adder cin=$add~446^ADD~5-25[0] b=unconn a=$dffe~447^Q~25 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[55] \ + cout=$add~446^ADD~5-26[0] + + +.subckt adder cin=$add~446^ADD~5-26[0] b=unconn a=$dffe~447^Q~26 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[56] \ + cout=$add~446^ADD~5-27[0] + + +.subckt adder cin=$add~446^ADD~5-27[0] b=unconn a=$dffe~447^Q~27 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[57] \ + cout=$add~446^ADD~5-28[0] + + +.subckt adder cin=$add~446^ADD~5-28[0] b=unconn a=$dffe~447^Q~28 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[58] \ + cout=$add~446^ADD~5-29[0] + + +.subckt adder cin=$add~446^ADD~5-29[0] b=unconn a=$dffe~447^Q~29 sumout=$auto$hard_block.cc:122:cell_hard_block$2625.B[59] \ + cout=$add~446^ADD~5-30[0] + + +.subckt adder cin=gnd b=gnd a=vcc sumout=$add~482^ADD~4-0~dummy_output~0~1 cout=$add~482^ADD~4-0[0] + + +.subckt adder cin=gnd b=gnd a=vcc sumout=$add~446^ADD~5-0~dummy_output~0~1 cout=$add~446^ADD~5-0[0] + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$mux~594^Y~0 data2=boot_idata~0 addr1[0]=$mux~445^Y~0 addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 \ + addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 \ + addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn addr1[12]=unconn addr1[13]=unconn \ + addr1[14]=unconn out2=dual_port_ram^MEM~3-0^out2~1 out1=dual_port_ram^MEM~3-0^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[29] data2=boot_idata~31 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-31^out2~1 out1=dual_port_ram^MEM~3-31^out1~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~31 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-31^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~31 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-31^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[0] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-0^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[1] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-1^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[2] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-2^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[3] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-3^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[4] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-4^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[5] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-5^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[6] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-6^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[7] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-7^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[8] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-8^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[9] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-9^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[10] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-10^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[11] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-11^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[12] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-12^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[13] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-13^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[14] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-14^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[15] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-15^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[16] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-16^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[17] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-17^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[18] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-18^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[19] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-19^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[20] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-20^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[21] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-21^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[22] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-22^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[23] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-23^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[24] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-24^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[25] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-25^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[26] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-26^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[27] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-27^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[28] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-28^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[29] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-29^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[30] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-30^out~0 + + +.subckt single_port_ram clk=clk data=$auto$hard_block.cc:122:cell_hard_block$2657.Y[31] we=$and~420^Y~0 addr[0]=$xor~273^Y~0 \ + addr[1]=$xor~350^Y~0 addr[2]=$xor~371^Y~0 addr[3]=$xor~378^Y~0 addr[4]=$xor~385^Y~0 addr[5]=$xor~392^Y~0 addr[6]=$xor~399^Y~0 \ + addr[7]=$xor~406^Y~0 addr[8]=$xor~203^Y~0 addr[9]=gnd addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn \ + addr[14]=unconn out=single_port_ram^MEM~0-31^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~0 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-0^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~1 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-1^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~2 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-2^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~3 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-3^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~4 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-4^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~5 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-5^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~6 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-6^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~7 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-7^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~8 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-8^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~9 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-9^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~10 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-10^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~11 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-11^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~12 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-12^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~13 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-13^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~14 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-14^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~15 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-15^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~16 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-16^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~17 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-17^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~18 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-18^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~19 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-19^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~20 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-20^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~21 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-21^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~22 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-22^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~23 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-23^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~24 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-24^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~25 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-25^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~26 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-26^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~27 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-27^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~28 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-28^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~29 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-29^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~30 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~2-30^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~0 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-0^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~1 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-1^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~2 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-2^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~3 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-3^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~4 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-4^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~5 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-5^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~6 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-6^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~7 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-7^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~8 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-8^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~9 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-9^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~10 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-10^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~11 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-11^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~12 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-12^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~13 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-13^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~14 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-14^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~15 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-15^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~16 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-16^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~17 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-17^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~18 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-18^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~19 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-19^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~20 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-20^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~21 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-21^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~22 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-22^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~23 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-23^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~24 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-24^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~25 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-25^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~26 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-26^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~27 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-27^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~28 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-28^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~29 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-29^out~0 + + +.subckt single_port_ram clk=clk data=$mux~605^Y~30 we=$and~492^Y~0 addr[0]=$sdffe~491^Q~0 addr[1]=$sdffe~491^Q~1 \ + addr[2]=$sdffe~491^Q~2 addr[3]=$sdffe~491^Q~3 addr[4]=$sdffe~491^Q~4 addr[5]=unconn addr[6]=unconn addr[7]=unconn \ + addr[8]=unconn addr[9]=unconn addr[10]=unconn addr[11]=unconn addr[12]=unconn addr[13]=unconn addr[14]=unconn \ + out=single_port_ram^MEM~1-30^out~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$mux~594^Y~1 data2=boot_idata~1 addr1[0]=$mux~445^Y~0 addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 \ + addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 \ + addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn addr1[12]=unconn addr1[13]=unconn \ + addr1[14]=unconn out2=dual_port_ram^MEM~3-1^out2~1 out1=dual_port_ram^MEM~3-1^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[0] data2=boot_idata~2 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-2^out2~1 out1=dual_port_ram^MEM~3-2^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[1] data2=boot_idata~3 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-3^out2~1 out1=dual_port_ram^MEM~3-3^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[2] data2=boot_idata~4 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-4^out2~1 out1=dual_port_ram^MEM~3-4^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[3] data2=boot_idata~5 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-5^out2~1 out1=dual_port_ram^MEM~3-5^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[4] data2=boot_idata~6 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-6^out2~1 out1=dual_port_ram^MEM~3-6^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[5] data2=boot_idata~7 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-7^out2~1 out1=dual_port_ram^MEM~3-7^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[6] data2=boot_idata~8 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-8^out2~1 out1=dual_port_ram^MEM~3-8^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[7] data2=boot_idata~9 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-9^out2~1 out1=dual_port_ram^MEM~3-9^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[8] data2=boot_idata~10 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-10^out2~1 out1=dual_port_ram^MEM~3-10^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[9] data2=boot_idata~11 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-11^out2~1 out1=dual_port_ram^MEM~3-11^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[10] data2=boot_idata~12 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-12^out2~1 out1=dual_port_ram^MEM~3-12^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[11] data2=boot_idata~13 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-13^out2~1 out1=dual_port_ram^MEM~3-13^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[12] data2=boot_idata~14 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-14^out2~1 out1=dual_port_ram^MEM~3-14^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[13] data2=boot_idata~15 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-15^out2~1 out1=dual_port_ram^MEM~3-15^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[14] data2=boot_idata~16 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-16^out2~1 out1=dual_port_ram^MEM~3-16^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[15] data2=boot_idata~17 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-17^out2~1 out1=dual_port_ram^MEM~3-17^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[16] data2=boot_idata~18 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-18^out2~1 out1=dual_port_ram^MEM~3-18^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[17] data2=boot_idata~19 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-19^out2~1 out1=dual_port_ram^MEM~3-19^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[18] data2=boot_idata~20 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-20^out2~1 out1=dual_port_ram^MEM~3-20^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[19] data2=boot_idata~21 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-21^out2~1 out1=dual_port_ram^MEM~3-21^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[20] data2=boot_idata~22 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-22^out2~1 out1=dual_port_ram^MEM~3-22^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[21] data2=boot_idata~23 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-23^out2~1 out1=dual_port_ram^MEM~3-23^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[22] data2=boot_idata~24 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-24^out2~1 out1=dual_port_ram^MEM~3-24^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[23] data2=boot_idata~25 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-25^out2~1 out1=dual_port_ram^MEM~3-25^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[24] data2=boot_idata~26 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-26^out2~1 out1=dual_port_ram^MEM~3-26^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[25] data2=boot_idata~27 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-27^out2~1 out1=dual_port_ram^MEM~3-27^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[26] data2=boot_idata~28 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-28^out2~1 out1=dual_port_ram^MEM~3-28^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[27] data2=boot_idata~29 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-29^out2~1 out1=dual_port_ram^MEM~3-29^out1~0 + + +.subckt dual_port_ram clk=clk we1=gnd we2=boot_iwe addr2[0]=boot_iaddr~0 addr2[1]=boot_iaddr~1 addr2[2]=boot_iaddr~2 \ + addr2[3]=boot_iaddr~3 addr2[4]=boot_iaddr~4 addr2[5]=boot_iaddr~5 addr2[6]=boot_iaddr~6 addr2[7]=boot_iaddr~7 \ + addr2[8]=boot_iaddr~8 addr2[9]=boot_iaddr~9 addr2[10]=unconn addr2[11]=unconn addr2[12]=unconn addr2[13]=unconn \ + addr2[14]=unconn data1=$auto$hard_block.cc:122:cell_hard_block$2625.A[28] data2=boot_idata~30 addr1[0]=$mux~445^Y~0 \ + addr1[1]=$mux~445^Y~1 addr1[2]=$mux~445^Y~2 addr1[3]=$mux~445^Y~3 addr1[4]=$mux~445^Y~4 addr1[5]=$mux~445^Y~5 \ + addr1[6]=$mux~445^Y~6 addr1[7]=$mux~445^Y~7 addr1[8]=$mux~445^Y~8 addr1[9]=$mux~445^Y~9 addr1[10]=unconn addr1[11]=unconn \ + addr1[12]=unconn addr1[13]=unconn addr1[14]=unconn out2=dual_port_ram^MEM~3-30^out2~1 out1=dual_port_ram^MEM~3-30^out1~0 + + +.subckt multiply b[0]=nop7_q~0 b[1]=nop7_q~1 b[2]=nop7_q~2 b[3]=nop7_q~3 b[4]=nop7_q~4 b[5]=nop7_q~5 b[6]=nop7_q~6 \ + b[7]=nop7_q~7 b[8]=nop7_q~8 b[9]=nop7_q~9 b[10]=nop7_q~10 b[11]=nop7_q~11 b[12]=nop7_q~12 b[13]=nop7_q~13 b[14]=nop7_q~14 \ + b[15]=nop7_q~15 b[16]=nop7_q~16 b[17]=nop7_q~17 b[18]=nop7_q~18 b[19]=nop7_q~19 b[20]=nop7_q~20 b[21]=nop7_q~21 \ + b[22]=nop7_q~22 b[23]=nop7_q~23 b[24]=nop7_q~24 b[25]=nop7_q~25 b[26]=nop7_q~26 b[27]=nop7_q~27 b[28]=nop7_q~28 \ + b[29]=nop7_q~29 b[30]=nop7_q~30 b[31]=nop7_q~31 b[32]=unconn b[33]=unconn b[34]=unconn b[35]=unconn a[0]=$mux~596^Y~0 \ + a[1]=$mux~596^Y~1 a[2]=$mux~596^Y~2 a[3]=$mux~596^Y~3 a[4]=$mux~596^Y~4 a[5]=$mux~596^Y~5 a[6]=$mux~596^Y~6 a[7]=$mux~596^Y~7 \ + a[8]=$mux~596^Y~8 a[9]=$mux~596^Y~9 a[10]=$mux~596^Y~10 a[11]=$mux~596^Y~11 a[12]=$mux~596^Y~12 a[13]=$mux~596^Y~13 \ + a[14]=$mux~596^Y~14 a[15]=$mux~596^Y~15 a[16]=$mux~596^Y~16 a[17]=$mux~596^Y~17 a[18]=$mux~596^Y~18 a[19]=$mux~596^Y~19 \ + a[20]=$mux~596^Y~20 a[21]=$mux~596^Y~21 a[22]=$mux~596^Y~22 a[23]=$mux~596^Y~23 a[24]=$mux~596^Y~24 a[25]=$mux~596^Y~25 \ + a[26]=$mux~596^Y~26 a[27]=$mux~596^Y~27 a[28]=$mux~596^Y~28 a[29]=$mux~596^Y~29 a[30]=$mux~596^Y~30 a[31]=$mux~596^Y~31 \ + a[32]=unconn a[33]=unconn a[34]=unconn a[35]=unconn out[0]=$mul~477[0] out[1]=$mul~477[1] out[2]=$mul~477[2] \ + out[3]=$mul~477[3] out[4]=$mul~477[4] out[5]=$mul~477[5] out[6]=$mul~477[6] out[7]=$mul~477[7] out[8]=$mul~477[8] \ + out[9]=$mul~477[9] out[10]=$mul~477[10] out[11]=$mul~477[11] out[12]=$mul~477[12] out[13]=$mul~477[13] out[14]=$mul~477[14] \ + out[15]=$mul~477[15] out[16]=$mul~477[16] out[17]=$mul~477[17] out[18]=$mul~477[18] out[19]=$mul~477[19] out[20]=$mul~477[20] \ + out[21]=$mul~477[21] out[22]=$mul~477[22] out[23]=$mul~477[23] out[24]=$mul~477[24] out[25]=$mul~477[25] out[26]=$mul~477[26] \ + out[27]=$mul~477[27] out[28]=$mul~477[28] out[29]=$mul~477[29] out[30]=$mul~477[30] out[31]=$mul~477[31] out[32]=$mul~477[32] \ + out[33]=$mul~477[33] out[34]=$mul~477[34] out[35]=$mul~477[35] out[36]=$mul~477[36] out[37]=$mul~477[37] out[38]=$mul~477[38] \ + out[39]=$mul~477[39] out[40]=$mul~477[40] out[41]=$mul~477[41] out[42]=$mul~477[42] out[43]=$mul~477[43] out[44]=$mul~477[44] \ + out[45]=$mul~477[45] out[46]=$mul~477[46] out[47]=$mul~477[47] out[48]=$mul~477[48] out[49]=$mul~477[49] out[50]=$mul~477[50] \ + out[51]=$mul~477[51] out[52]=$mul~477[52] out[53]=$mul~477[53] out[54]=$mul~477[54] out[55]=$mul~477[55] out[56]=$mul~477[56] \ + out[57]=$mul~477[57] out[58]=$mul~477[58] out[59]=$mul~477[59] out[60]=$mul~477[60] out[61]=$mul~477[61] out[62]=$mul~477[62] \ + out[63]=$mul~477[63] out[64]=$mul~477[64] out[65]=$mul~477[65] out[66]=$mul~477[66] out[67]=$mul~477[67] out[68]=$mul~477[68] \ + out[69]=$mul~477[69] out[70]=$mul~477[70] out[71]=$mul~477[71] + + + + +.names $sdffe~487^Q~31 single_port_ram^MEM~2-31^out~0 $sdffe~489^Q~0 nop7_q~31 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~30 single_port_ram^MEM~2-30^out~0 $sdffe~489^Q~0 nop7_q~30 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~21 single_port_ram^MEM~2-21^out~0 $sdffe~489^Q~0 nop7_q~21 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~20 single_port_ram^MEM~2-20^out~0 $sdffe~489^Q~0 nop7_q~20 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~29 single_port_ram^MEM~2-29^out~0 $sdffe~489^Q~0 nop7_q~29 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~19 single_port_ram^MEM~2-19^out~0 $sdffe~489^Q~0 nop7_q~19 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~18 single_port_ram^MEM~2-18^out~0 $sdffe~489^Q~0 nop7_q~18 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~28 single_port_ram^MEM~2-28^out~0 $sdffe~489^Q~0 nop7_q~28 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~17 single_port_ram^MEM~2-17^out~0 $sdffe~489^Q~0 nop7_q~17 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~16 single_port_ram^MEM~2-16^out~0 $sdffe~489^Q~0 nop7_q~16 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~27 single_port_ram^MEM~2-27^out~0 $sdffe~489^Q~0 nop7_q~27 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~15 single_port_ram^MEM~2-15^out~0 $sdffe~489^Q~0 nop7_q~15 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~26 single_port_ram^MEM~2-26^out~0 $sdffe~489^Q~0 nop7_q~26 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~14 single_port_ram^MEM~2-14^out~0 $sdffe~489^Q~0 nop7_q~14 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~25 single_port_ram^MEM~2-25^out~0 $sdffe~489^Q~0 nop7_q~25 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~13 single_port_ram^MEM~2-13^out~0 $sdffe~489^Q~0 nop7_q~13 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~12 single_port_ram^MEM~2-12^out~0 $sdffe~489^Q~0 nop7_q~12 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~24 single_port_ram^MEM~2-24^out~0 $sdffe~489^Q~0 nop7_q~24 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~11 single_port_ram^MEM~2-11^out~0 $sdffe~489^Q~0 nop7_q~11 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~23 single_port_ram^MEM~2-23^out~0 $sdffe~489^Q~0 nop7_q~23 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~10 single_port_ram^MEM~2-10^out~0 $sdffe~489^Q~0 nop7_q~10 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~9 single_port_ram^MEM~2-9^out~0 $sdffe~489^Q~0 nop7_q~9 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~22 single_port_ram^MEM~2-22^out~0 $sdffe~489^Q~0 nop7_q~22 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~8 single_port_ram^MEM~2-8^out~0 $sdffe~489^Q~0 nop7_q~8 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~7 single_port_ram^MEM~2-7^out~0 $sdffe~489^Q~0 nop7_q~7 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~6 single_port_ram^MEM~2-6^out~0 $sdffe~489^Q~0 nop7_q~6 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~0 single_port_ram^MEM~2-0^out~0 $sdffe~489^Q~0 nop7_q~0 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~1 single_port_ram^MEM~2-1^out~0 $sdffe~489^Q~0 nop7_q~1 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~2 single_port_ram^MEM~2-2^out~0 $sdffe~489^Q~0 nop7_q~2 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~3 single_port_ram^MEM~2-3^out~0 $sdffe~489^Q~0 nop7_q~3 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~4 single_port_ram^MEM~2-4^out~0 $sdffe~489^Q~0 nop7_q~4 +-10 1 +1-1 1 + + +.names $sdffe~487^Q~5 single_port_ram^MEM~2-5^out~0 $sdffe~489^Q~0 nop7_q~5 +-10 1 +1-1 1 + + +.names new_n1492 $dff~79^Q~1 $dff~79^Q~2 $mux~594^Y~0 +000 1 + + +.names $sdffe~487^Q~0 single_port_ram^MEM~1-0^out~0 $sdffe~488^Q~0 new_n1492 +-00 1 +0-1 1 + + +.names $auto$hard_block.cc:122:cell_hard_block$2625.A[0] lo081 new_n1494_1 $mux~445^Y~0 +1-0 1 +-11 1 + + +.names new_n1543 $dffe~3^Q~0 new_n1495_1 $dff~83^Q~1 $dff~83^Q~4 $dffe~6^Q~0 new_n1494_1 +-----1 0 +-1010- 0 +110-0- 0 +-11-1- 0 +1110-- 0 + + +.names new_n1496 new_n1521 new_n1529 new_n1538 new_n1540 new_n1495_1 +11111 1 + + +.names nop7_q~9 nop7_q~6 new_n1520_1 new_n1519_1 new_n1509_1 new_n1497 new_n1496 +110011 1 +101011 1 +010111 1 +001111 1 + + +.names nop7_q~21 nop7_q~23 new_n1502 new_n1508 new_n1505_1 new_n1498 new_n1497 +-----0 0 +----0- 0 +-0-0-- 0 +1-1--- 0 + + +.names nop7_q~30 nop7_q~25 new_n1503 new_n1504_1 new_n1499_1 new_n1498 +11001 1 +10101 1 +01011 1 +00111 1 + + +.names nop7_q~22 new_n1501 nop7_q~21 new_n1502 new_n1500_1 nop7_q~20 new_n1499_1 +----00 0 +----11 0 +--00-- 0 +11---- 0 + + +.names $sdffe~487^Q~20 single_port_ram^MEM~1-20^out~0 $sdffe~488^Q~0 new_n1500_1 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~22 single_port_ram^MEM~1-22^out~0 $sdffe~488^Q~0 new_n1501 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~21 single_port_ram^MEM~1-21^out~0 $sdffe~488^Q~0 new_n1502 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~25 single_port_ram^MEM~1-25^out~0 $sdffe~488^Q~0 new_n1503 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~30 single_port_ram^MEM~1-30^out~0 $sdffe~488^Q~0 new_n1504_1 +-00 1 +0-1 1 + + +.names nop7_q~10 new_n1507 nop7_q~16 new_n1506 new_n1505_1 +--00 0 +00-- 0 + + +.names $sdffe~487^Q~16 single_port_ram^MEM~1-16^out~0 $sdffe~488^Q~0 new_n1506 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~10 single_port_ram^MEM~1-10^out~0 $sdffe~488^Q~0 new_n1507 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~23 single_port_ram^MEM~1-23^out~0 $sdffe~488^Q~0 new_n1508 +-00 1 +0-1 1 + + +.names nop7_q~18 nop7_q~17 new_n1518 new_n1517 new_n1514_1 new_n1510_1 new_n1509_1 +110011 1 +101011 1 +010111 1 +001111 1 + + +.names nop7_q~15 new_n1511 nop7_q~2 new_n1512 nop7_q~4 new_n1513 new_n1510_1 +----00 0 +----11 0 +--00-- 0 +--11-- 0 +00---- 0 +11---- 0 + + +.names $sdffe~487^Q~15 single_port_ram^MEM~1-15^out~0 $sdffe~488^Q~0 new_n1511 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~2 single_port_ram^MEM~1-2^out~0 $sdffe~488^Q~0 new_n1512 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~4 single_port_ram^MEM~1-4^out~0 $sdffe~488^Q~0 new_n1513 +-00 1 +0-1 1 + + +.names nop7_q~8 new_n1516 new_n1492 nop7_q~0 new_n1515_1 nop7_q~5 new_n1514_1 +----00 0 +----11 0 +--00-- 0 +--11-- 0 +00---- 0 +11---- 0 + + +.names $sdffe~487^Q~5 single_port_ram^MEM~1-5^out~0 $sdffe~488^Q~0 new_n1515_1 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~8 single_port_ram^MEM~1-8^out~0 $sdffe~488^Q~0 new_n1516 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~18 single_port_ram^MEM~1-18^out~0 $sdffe~488^Q~0 new_n1517 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~17 single_port_ram^MEM~1-17^out~0 $sdffe~488^Q~0 new_n1518 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~9 single_port_ram^MEM~1-9^out~0 $sdffe~488^Q~0 new_n1519_1 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~6 single_port_ram^MEM~1-6^out~0 $sdffe~488^Q~0 new_n1520_1 +-00 1 +0-1 1 + + +.names nop7_q~12 nop7_q~7 new_n1528 new_n1527 new_n1526 new_n1522 new_n1521 +110011 1 +101011 1 +010111 1 +001111 1 + + +.names nop7_q~31 new_n1523 nop7_q~1 new_n1524_1 nop7_q~3 new_n1525_1 new_n1522 +----00 0 +----11 0 +--00-- 0 +--11-- 0 +00---- 0 +11---- 0 + + +.names $sdffe~487^Q~31 single_port_ram^MEM~1-31^out~0 $sdffe~488^Q~0 new_n1523 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~1 single_port_ram^MEM~1-1^out~0 $sdffe~488^Q~0 new_n1524_1 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~3 single_port_ram^MEM~1-3^out~0 $sdffe~488^Q~0 new_n1525_1 +-00 1 +0-1 1 + + +.names new_n1501 nop7_q~22 nop7_q~16 new_n1506 new_n1526 +--11 0 +00-- 0 + + +.names $sdffe~487^Q~12 single_port_ram^MEM~1-12^out~0 $sdffe~488^Q~0 new_n1527 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~7 single_port_ram^MEM~1-7^out~0 $sdffe~488^Q~0 new_n1528 +-00 1 +0-1 1 + + +.names nop7_q~14 nop7_q~13 new_n1537 new_n1536 new_n1533 new_n1530 new_n1529 +110011 1 +101011 1 +010111 1 +001111 1 + + +.names nop7_q~26 nop7_q~24 new_n1531 new_n1532 new_n1530 +0--0 0 +1--1 0 +-00- 0 +-11- 0 + + +.names $sdffe~487^Q~24 single_port_ram^MEM~1-24^out~0 $sdffe~488^Q~0 new_n1531 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~26 single_port_ram^MEM~1-26^out~0 $sdffe~488^Q~0 new_n1532 +-00 1 +0-1 1 + + +.names nop7_q~10 new_n1507 nop7_q~28 new_n1534 nop7_q~11 new_n1535 new_n1533 +----00 0 +----11 0 +--00-- 0 +11---- 0 + + +.names $sdffe~487^Q~28 single_port_ram^MEM~1-28^out~0 $sdffe~488^Q~0 new_n1534 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~11 single_port_ram^MEM~1-11^out~0 $sdffe~488^Q~0 new_n1535 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~14 single_port_ram^MEM~1-14^out~0 $sdffe~488^Q~0 new_n1536 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~13 single_port_ram^MEM~1-13^out~0 $sdffe~488^Q~0 new_n1537 +-00 1 +0-1 1 + + +.names nop7_q~23 new_n1508 nop7_q~28 new_n1534 new_n1539 nop7_q~19 new_n1538 +----00 0 +----11 0 +--11-- 0 +11---- 0 + + +.names $sdffe~487^Q~19 single_port_ram^MEM~1-19^out~0 $sdffe~488^Q~0 new_n1539 +-00 1 +0-1 1 + + +.names nop7_q~29 nop7_q~27 new_n1541 new_n1542 new_n1540 +0--0 0 +1--1 0 +-00- 0 +-11- 0 + + +.names $sdffe~487^Q~27 single_port_ram^MEM~1-27^out~0 $sdffe~488^Q~0 new_n1541 +-00 1 +0-1 1 + + +.names $sdffe~487^Q~29 single_port_ram^MEM~1-29^out~0 $sdffe~488^Q~0 new_n1542 +-00 1 +0-1 1 + + +.names $dff~83^Q~3 new_n1544 new_n1523 $dff~83^Q~2 $dff~83^Q~5 new_n1543 +--000 0 +--110 0 +011-0 0 +-01-1 0 + + +.names new_n1545 new_n1548 new_n1551 new_n1507 new_n1537 new_n1544 +11111 1 + + +.names new_n1546 new_n1547 new_n1541 new_n1542 new_n1531 new_n1532 new_n1545 +111111 1 + + +.names new_n1525_1 new_n1512 new_n1546 +11 1 + + +.names new_n1492 new_n1513 new_n1547 +11 1 + + +.names new_n1549 new_n1550 new_n1501 new_n1524_1 new_n1502 new_n1548 +11111 1 + + +.names new_n1516 new_n1519_1 new_n1500_1 new_n1520_1 new_n1506 new_n1518 new_n1549 +111111 1 + + +.names new_n1527 new_n1511 new_n1539 new_n1528 new_n1517 new_n1508 new_n1550 +111111 1 + + +.names new_n1515_1 new_n1534 new_n1503 new_n1536 new_n1535 new_n1504_1 new_n1551 +111111 1 + + +.names lo175 new_n1512 $add~482^ADD~4-1[1] $dff~79^Q~2 $dff~79^Q~1 $auto$hard_block.cc:122:cell_hard_block$2625.A[0] +-0-00 1 +1--10 1 +--1-1 1 + + +.names $auto$hard_block.cc:122:cell_hard_block$2625.A[1] lo082 new_n1494_1 $mux~445^Y~1 +1-0 1 +-11 1 + + +.names lo176 new_n1525_1 $add~482^ADD~4-2[1] $dff~79^Q~2 $dff~79^Q~1 $auto$hard_block.cc:122:cell_hard_block$2625.A[1] +-0-00 1 +1--10 1 +--1-1 1 + + +.names $auto$hard_block.cc:122:cell_hard_block$2625.A[2] lo083 new_n1494_1 $mux~445^Y~2 +1-0 1 +-11 1 + + +.names lo177 new_n1513 $add~482^ADD~4-3[1] $dff~79^Q~2 $dff~79^Q~1 $auto$hard_block.cc:122:cell_hard_block$2625.A[2] +-0-00 1 +1--10 1 +--1-1 1 + + +.names $auto$hard_block.cc:122:cell_hard_block$2625.A[3] lo084 new_n1494_1 $mux~445^Y~3 +1-0 1 +-11 1 + + +.names lo178 new_n1515_1 $add~482^ADD~4-4[1] $dff~79^Q~2 $dff~79^Q~1 $auto$hard_block.cc:122:cell_hard_block$2625.A[3] +-0-00 1 +1--10 1 +--1-1 1 + + +.names $auto$hard_block.cc:122:cell_hard_block$2625.A[4] lo085 new_n1494_1 $mux~445^Y~4 +1-0 1 +-11 1 + + +.names lo179 new_n1520_1 $add~482^ADD~4-5[1] $dff~79^Q~2 $dff~79^Q~1 $auto$hard_block.cc:122:cell_hard_block$2625.A[4] +-0-00 1 +1--10 1 +--1-1 1 + + +.names $auto$hard_block.cc:122:cell_hard_block$2625.A[5] lo086 new_n1494_1 $mux~445^Y~5 +1-0 1 +-11 1 + + +.names lo180 new_n1528 $add~482^ADD~4-6[1] $dff~79^Q~2 $dff~79^Q~1 $auto$hard_block.cc:122:cell_hard_block$2625.A[5] +-0-00 1 +1--10 1 +--1-1 1 + + +.names $auto$hard_block.cc:122:cell_hard_block$2625.A[6] lo087 new_n1494_1 $mux~445^Y~6 +1-0 1 +-11 1 + + +.names lo181 new_n1516 $add~482^ADD~4-7[1] $dff~79^Q~2 $dff~79^Q~1 $auto$hard_block.cc:122:cell_hard_block$2625.A[6] +-0-00 1 +1--10 1 +--1-1 1 + + +.names $auto$hard_block.cc:122:cell_hard_block$2625.A[7] lo088 new_n1494_1 $mux~445^Y~7 +1-0 1 +-11 1 + + +.names lo182 new_n1519_1 $add~482^ADD~4-8[1] $dff~79^Q~2 $dff~79^Q~1 $auto$hard_block.cc:122:cell_hard_block$2625.A[7] +-0-00 1 +1--10 1 +--1-1 1 + + +.names $auto$hard_block.cc:122:cell_hard_block$2625.A[8] lo089 new_n1494_1 $mux~445^Y~8 +1-0 1 +-11 1 + + +.names lo183 new_n1507 $add~482^ADD~4-9[1] $dff~79^Q~2 $dff~79^Q~1 $auto$hard_block.cc:122:cell_hard_block$2625.A[8] +-0-00 1 +1--10 1 +--1-1 1 + + +.names $auto$hard_block.cc:122:cell_hard_block$2625.A[9] lo090 new_n1494_1 $mux~445^Y~9 +1-0 1 +-11 1 + + +.names lo184 new_n1535 $add~482^ADD~4-10[1] $dff~79^Q~2 $dff~79^Q~1 $auto$hard_block.cc:122:cell_hard_block$2625.A[9] +-0-00 1 +1--10 1 +--1-1 1 + + +.names lo080 new_n1523 $add~482^ADD~4-30[1] $dff~79^Q~2 $dff~79^Q~1 $auto$hard_block.cc:122:cell_hard_block$2625.A[29] +-0-00 1 +1--10 1 +--1-1 1 + + +.names new_n1655_1 new_n1573 new_n1659 $dff~84^Q~3 $mux~605^Y~31 +-001 1 +-111 1 +1--- 1 + + +.names new_n1651 new_n1653 new_n1652 new_n1654_1 new_n1574 new_n1573 +---01 0 +--1-1 0 +--10- 0 +00-0- 0 +001-- 0 + + +.names new_n1575 new_n1646 new_n1649_1 new_n1648 new_n1650_1 new_n1647 new_n1574 +---101 1 +-00-01 1 +1---01 1 +-001-1 1 +1--1-1 1 + + +.names new_n1576 new_n1641 new_n1644_1 new_n1643 new_n1645_1 new_n1642 new_n1575 +---101 1 +-00-01 1 +1---01 1 +-001-1 1 +1--1-1 1 + + +.names new_n1577 new_n1636 new_n1639_1 new_n1638 new_n1640_1 new_n1637 new_n1576 +---101 1 +-00-01 1 +1---01 1 +-001-1 1 +1--1-1 1 + + +.names new_n1578 new_n1632 new_n1635_1 new_n1634_1 new_n1633 new_n1631 new_n1577 +--0011 1 +-1-011 1 +0-0-11 1 +01--11 1 +0-00-1 1 +01-0-1 1 +-10--1 1 + + +.names new_n1579 new_n1627 new_n1628 new_n1630_1 new_n1629_1 new_n1578 +--011 1 +1--11 1 +-00-1 1 +10--1 1 +1-01- 1 +-0-1- 1 +100-- 1 + + +.names new_n1580 new_n1623 new_n1624 new_n1626 new_n1625 new_n1579 +--011 1 +1--11 1 +-00-1 1 +10--1 1 +1-01- 1 +-0-1- 1 +100-- 1 + + +.names new_n1619_1 new_n1620_1 new_n1581 new_n1618 new_n1621 new_n1622 new_n1580 +--0011 1 +-1--11 1 +-100-1 1 +0----1 1 +0-001- 1 +01--1- 1 +0100-- 1 + + +.names new_n1582 new_n1614_1 new_n1615_1 new_n1616 new_n1617 new_n1612 new_n1581 +--0000 1 +-0-000 1 +0-0-00 1 +00--00 1 +0-00-0 1 +00-0-0 1 +-00--0 1 + + +.names new_n1608 new_n1610_1 new_n1583 new_n1607 new_n1611 new_n1609_1 new_n1582 +--0011 1 +-1--11 1 +-100-1 1 +1----1 1 +1-001- 1 +11--1- 1 +1100-- 1 + + +.names new_n1584 new_n1603 new_n1604_1 new_n1605_1 new_n1606 new_n1601 new_n1583 +--0000 1 +-0-000 1 +0-0-00 1 +00--00 1 +0-00-0 1 +00-0-0 1 +-00--0 1 + + +.names new_n1585 new_n1587 new_n1588 new_n1600 new_n1598 new_n1599 new_n1584 +----00 0 +-000-0 0 +1----0 0 +-0000- 0 +1---0- 0 + + +.names lo084 new_n1515_1 new_n1586 $dffe~10^Q~0 new_n1585 +-000 1 +1-01 1 + + +.names $dff~81^Q~0 lo180 nop7_q~5 $dff~81^Q~1 new_n1586 +--11 0 +11-- 0 + + +.names lo084 new_n1515_1 $dffe~10^Q~0 new_n1586 new_n1587 +-101 1 +0-11 1 + + +.names new_n1591 new_n1593 new_n1594 new_n1595 new_n1592 new_n1589 new_n1588 +--1110 1 +-1-110 1 +-11-10 1 +1---10 1 +1-11-0 1 +11-1-0 1 +111--0 1 + + +.names lo083 new_n1513 new_n1590 $dffe~10^Q~0 new_n1589 +-000 1 +1-01 1 + + +.names $sdffe~487^Q~4 single_port_ram^MEM~2-4^out~0 lo179 $dff~81^Q~0 $sdffe~489^Q~0 $dff~81^Q~1 new_n1590 +-1--01 0 +1---11 0 +--11-- 0 + + +.names $dff~81^Q~0 lo178 nop7_q~3 $dff~81^Q~1 new_n1591 +--11 0 +11-- 0 + + +.names lo082 new_n1525_1 $dffe~10^Q~0 new_n1592 +-10 1 +0-1 1 + + +.names $dff~81^Q~0 lo177 nop7_q~2 $dff~81^Q~1 new_n1593 +--11 0 +11-- 0 + + +.names lo081 new_n1512 $dffe~10^Q~0 new_n1594 +-10 1 +0-1 1 + + +.names new_n1596 new_n1492 new_n1524_1 new_n1597 $dffe~7^Q~0 $dffe~10^Q~0 new_n1595 +--0000 0 +-00-00 0 +00--00 0 +-000-0 0 +00-0-0 0 +0-0--0 0 +0--00- 0 + + +.names $sdffe~487^Q~1 single_port_ram^MEM~2-1^out~0 lo176 $dff~81^Q~0 $sdffe~489^Q~0 $dff~81^Q~1 new_n1596 +-1--01 0 +1---11 0 +--11-- 0 + + +.names $sdffe~487^Q~0 single_port_ram^MEM~2-0^out~0 lo175 $dff~81^Q~0 $sdffe~489^Q~0 $dff~81^Q~1 new_n1597 +-1--01 0 +1---11 0 +--11-- 0 + + +.names $dff~81^Q~0 lo181 nop7_q~6 $dff~81^Q~1 new_n1598 +--11 0 +11-- 0 + + +.names lo085 new_n1520_1 $dffe~10^Q~0 new_n1599 +-10 1 +0-1 1 + + +.names lo083 new_n1513 $dffe~10^Q~0 new_n1590 new_n1600 +-101 1 +0-11 1 + + +.names lo088 new_n1519_1 $dffe~10^Q~0 new_n1602 new_n1601 +-101 1 +0-11 1 + + +.names $dff~81^Q~0 lo184 nop7_q~9 $dff~81^Q~1 new_n1602 +--11 0 +11-- 0 + + +.names $dff~81^Q~0 lo183 nop7_q~8 $dff~81^Q~1 new_n1603 +--11 0 +11-- 0 + + +.names lo087 new_n1516 $dffe~10^Q~0 new_n1604_1 +-10 1 +0-1 1 + + +.names $dff~81^Q~0 lo182 nop7_q~7 $dff~81^Q~1 new_n1605_1 +--11 0 +11-- 0 + + +.names lo086 new_n1528 $dffe~10^Q~0 new_n1606 +-10 1 +0-1 1 + + +.names lo088 new_n1519_1 new_n1602 $dffe~10^Q~0 new_n1607 +-000 1 +1-01 1 + + +.names $dff~81^Q~0 lo186 nop7_q~11 $dff~81^Q~1 new_n1608 +--11 0 +11-- 0 + + +.names lo090 new_n1535 $dffe~10^Q~0 new_n1609_1 +-10 1 +0-1 1 + + +.names $dff~81^Q~0 lo185 nop7_q~10 $dff~81^Q~1 new_n1610_1 +--11 0 +11-- 0 + + +.names lo089 new_n1507 $dffe~10^Q~0 new_n1611 +-10 1 +0-1 1 + + +.names lo093 new_n1536 $dffe~10^Q~0 new_n1613 new_n1612 +-101 1 +0-11 1 + + +.names $dff~81^Q~0 lo189 nop7_q~14 $dff~81^Q~1 new_n1613 +--11 0 +11-- 0 + + +.names $dff~81^Q~0 lo188 nop7_q~13 $dff~81^Q~1 new_n1614_1 +--11 0 +11-- 0 + + +.names lo092 new_n1537 $dffe~10^Q~0 new_n1615_1 +-10 1 +0-1 1 + + +.names $dff~81^Q~0 lo187 nop7_q~12 $dff~81^Q~1 new_n1616 +--11 0 +11-- 0 + + +.names lo091 new_n1527 $dffe~10^Q~0 new_n1617 +-10 1 +0-1 1 + + +.names lo093 new_n1536 new_n1613 $dffe~10^Q~0 new_n1618 +-000 1 +1-01 1 + + +.names nop7_q~16 $dff~81^Q~1 new_n1619_1 +11 1 + + +.names $dff~81^Q~0 lo011 nop7_q~15 $dff~81^Q~1 new_n1620_1 +--11 0 +11-- 0 + + +.names lo094 new_n1511 $dffe~10^Q~0 new_n1621 +-10 1 +0-1 1 + + +.names lo095 new_n1506 $dffe~10^Q~0 new_n1622 +-10 1 +0-1 1 + + +.names nop7_q~18 $dff~81^Q~1 new_n1623 +11 1 + + +.names nop7_q~17 $dff~81^Q~1 new_n1624 +11 1 + + +.names lo096 new_n1518 $dffe~10^Q~0 new_n1625 +-10 1 +0-1 1 + + +.names lo097 new_n1517 $dffe~10^Q~0 new_n1626 +-10 1 +0-1 1 + + +.names nop7_q~20 $dff~81^Q~1 new_n1627 +11 1 + + +.names nop7_q~19 $dff~81^Q~1 new_n1628 +11 1 + + +.names lo098 new_n1539 $dffe~10^Q~0 new_n1629_1 +-10 1 +0-1 1 + + +.names lo099 new_n1500_1 $dffe~10^Q~0 new_n1630_1 +-10 1 +0-1 1 + + +.names nop7_q~23 $dff~81^Q~1 new_n1631 +11 1 + + +.names nop7_q~22 $dff~81^Q~1 new_n1632 +11 1 + + +.names nop7_q~21 $dff~81^Q~1 new_n1633 +11 1 + + +.names lo100 new_n1502 $dffe~10^Q~0 new_n1634_1 +-10 1 +0-1 1 + + +.names lo101 new_n1501 $dffe~10^Q~0 new_n1635_1 +-10 1 +0-1 1 + + +.names new_n1578 new_n1632 new_n1633 new_n1635_1 new_n1634_1 new_n1631 new_n1636 +--0110 1 +1--110 1 +-00-10 1 +10--10 1 +1-01-0 1 +-0-1-0 1 +100--0 1 + + +.names nop7_q~25 $dff~81^Q~1 new_n1637 +11 1 + + +.names nop7_q~24 $dff~81^Q~1 new_n1638 +11 1 + + +.names lo102 new_n1508 $dffe~10^Q~0 new_n1639_1 +-10 1 +0-1 1 + + +.names lo103 new_n1531 $dffe~10^Q~0 new_n1640_1 +-10 1 +0-1 1 + + +.names new_n1636 new_n1639_1 new_n1638 new_n1640_1 new_n1577 new_n1637 new_n1641 +-1-100 1 +1--100 1 +-10-00 1 +1-0-00 1 +--01-0 1 + + +.names nop7_q~27 $dff~81^Q~1 new_n1642 +11 1 + + +.names nop7_q~26 $dff~81^Q~1 new_n1643 +11 1 + + +.names lo104 new_n1503 $dffe~10^Q~0 new_n1644_1 +-10 1 +0-1 1 + + +.names lo105 new_n1532 $dffe~10^Q~0 new_n1645_1 +-10 1 +0-1 1 + + +.names new_n1641 new_n1644_1 new_n1643 new_n1645_1 new_n1576 new_n1642 new_n1646 +-1-100 1 +1--100 1 +-10-00 1 +1-0-00 1 +--01-0 1 + + +.names nop7_q~29 $dff~81^Q~1 new_n1647 +11 1 + + +.names nop7_q~28 $dff~81^Q~1 new_n1648 +11 1 + + +.names lo106 new_n1541 $dffe~10^Q~0 new_n1649_1 +-10 1 +0-1 1 + + +.names lo107 new_n1534 $dffe~10^Q~0 new_n1650_1 +-10 1 +0-1 1 + + +.names new_n1646 new_n1649_1 new_n1648 new_n1650_1 new_n1575 new_n1647 new_n1651 +-1-100 1 +1--100 1 +-10-00 1 +1-0-00 1 +--01-0 1 + + +.names nop7_q~30 $dff~81^Q~1 new_n1652 +11 1 + + +.names lo108 new_n1542 $dffe~10^Q~0 new_n1653 +-10 1 +0-1 1 + + +.names lo109 new_n1504_1 $dffe~10^Q~0 new_n1654_1 +-10 1 +0-1 1 + + +.names new_n1657 single_port_ram^MEM~0-31^out~0 new_n1656 new_n1658 new_n1655_1 +--11 1 +11-1 1 + + +.names nop7_q~31 $dff~81^Q~1 $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1523 \ + $auto$simplemap.cc:248:simplemap_eqne$4611[1] $dff~84^Q~1 new_n1656 +--1001 1 +11-001 1 +111-01 1 +-00011 1 +0-0011 1 +110111 1 +-01111 1 +0-1111 1 + + +.names $dff~84^Q~1 $dff~84^Q~6 $dff~84^Q~2 new_n1657 +001 1 + + +.names $dff~84^Q~3 $dff~84^Q~5 new_n1658 +00 1 + + +.names new_n1523 lo110 nop7_q~31 $dff~81^Q~1 $dffe~10^Q~0 new_n1659 +0--00 1 +1-110 1 +0-0-0 1 +-1-01 1 +-0111 1 +-10-1 1 + + +.names new_n1661 $dffe~2^Q~0 $and~492^Y~0 +01 1 + + +.names lo023 lo024 lo025 lo026 lo027 new_n1661 +00000 1 + + +.names new_n1663 nop7_q~0 $auto$hard_block.cc:122:cell_hard_block$2657.Y[0] +01 1 + + +.names new_n1666 new_n1665 new_n1664 new_n1663 +--0 0 +11- 0 + + +.names $auto$simplemap.cc:248:simplemap_eqne$3524[1] new_n1665 $dffe~8^Q~0 new_n1664 +--0 0 +01- 0 + + +.names new_n1492 $dffe~10^Q~0 new_n1597 $dffe~7^Q~0 new_n1524_1 new_n1596 new_n1665 +-00000 1 +00-000 1 +000-00 1 +--1110 1 +1--110 1 +1-1-10 1 +-1-1-0 1 +-11--0 1 +-01101 1 +10-101 1 +101-01 1 +--0011 1 +00-011 1 +000-11 1 +-100-1 1 + + +.names new_n1492 $dffe~10^Q~0 new_n1597 $dffe~7^Q~0 new_n1666 +0000 1 +-110 1 +1-10 1 +-101 1 +1-01 1 +0011 1 + + +.names new_n1573 new_n1659 $dffe~8^Q~3 $and~420^Y~0 +101 1 +011 1 + + +.names new_n1593 new_n1594 new_n1595 $xor~273^Y~0 +000 1 +110 1 +101 1 +011 1 + + +.names new_n1670 new_n1591 new_n1592 $xor~350^Y~0 +000 1 +110 1 +101 1 +011 1 + + +.names new_n1593 new_n1594 new_n1595 new_n1670 +-11 1 +1-1 1 +11- 1 + + +.names new_n1670 new_n1600 new_n1589 new_n1591 new_n1592 $xor~371^Y~0 +--100 1 +-1-00 1 +0-1-0 1 +01--0 1 +-0011 1 +100-1 1 +0-10- 1 +01-0- 1 +1001- 1 + + +.names new_n1585 new_n1587 new_n1673 $xor~378^Y~0 +000 1 +-11 1 +1-1 1 + + +.names new_n1588 new_n1600 new_n1673 +00 1 + + +.names new_n1673 new_n1587 new_n1585 new_n1598 new_n1599 $xor~385^Y~0 +--100 1 +10-00 1 +-1010 1 +0-010 1 +-1001 1 +0-001 1 +--111 1 +10-11 1 + + +.names new_n1584 new_n1605_1 new_n1606 $xor~392^Y~0 +000 1 +110 1 +101 1 +011 1 + + +.names new_n1677 new_n1603 new_n1604_1 $xor~399^Y~0 +000 1 +110 1 +101 1 +011 1 + + +.names new_n1584 new_n1605_1 new_n1606 new_n1677 +-11 1 +1-1 1 +11- 1 + + +.names new_n1677 new_n1607 new_n1601 new_n1603 new_n1604_1 $xor~406^Y~0 +--100 1 +-1-00 1 +0-1-0 1 +01--0 1 +-0011 1 +100-1 1 +0-10- 1 +01-0- 1 +1001- 1 + + +.names new_n1680 new_n1610_1 new_n1611 $xor~203^Y~0 +000 1 +110 1 +101 1 +011 1 + + +.names new_n1583 new_n1607 new_n1680 +00 1 + + +.names new_n1663 nop7_q~1 $auto$hard_block.cc:122:cell_hard_block$2657.Y[1] +01 1 + + +.names new_n1663 nop7_q~2 $auto$hard_block.cc:122:cell_hard_block$2657.Y[2] +01 1 + + +.names new_n1663 nop7_q~3 $auto$hard_block.cc:122:cell_hard_block$2657.Y[3] +01 1 + + +.names new_n1663 nop7_q~4 $auto$hard_block.cc:122:cell_hard_block$2657.Y[4] +01 1 + + +.names new_n1663 nop7_q~5 $auto$hard_block.cc:122:cell_hard_block$2657.Y[5] +01 1 + + +.names new_n1663 nop7_q~6 $auto$hard_block.cc:122:cell_hard_block$2657.Y[6] +01 1 + + +.names new_n1663 nop7_q~7 $auto$hard_block.cc:122:cell_hard_block$2657.Y[7] +01 1 + + +.names new_n1689 nop7_q~0 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~8 new_n1664 \ + $auto$hard_block.cc:122:cell_hard_block$2657.Y[8] +---10 1 +111-- 1 + + +.names new_n1666 new_n1665 new_n1689 +01 1 + + +.names new_n1689 nop7_q~1 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~9 new_n1664 \ + $auto$hard_block.cc:122:cell_hard_block$2657.Y[9] +---10 1 +111-- 1 + + +.names new_n1689 nop7_q~2 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~10 new_n1664 \ + $auto$hard_block.cc:122:cell_hard_block$2657.Y[10] +---10 1 +111-- 1 + + +.names new_n1689 nop7_q~3 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~11 new_n1664 \ + $auto$hard_block.cc:122:cell_hard_block$2657.Y[11] +---10 1 +111-- 1 + + +.names new_n1689 nop7_q~4 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~12 new_n1664 \ + $auto$hard_block.cc:122:cell_hard_block$2657.Y[12] +---10 1 +111-- 1 + + +.names new_n1689 nop7_q~5 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~13 new_n1664 \ + $auto$hard_block.cc:122:cell_hard_block$2657.Y[13] +---10 1 +111-- 1 + + +.names new_n1689 nop7_q~6 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~14 new_n1664 \ + $auto$hard_block.cc:122:cell_hard_block$2657.Y[14] +---10 1 +111-- 1 + + +.names new_n1689 nop7_q~7 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~15 new_n1664 \ + $auto$hard_block.cc:122:cell_hard_block$2657.Y[15] +---10 1 +111-- 1 + + +.names $dffe~8^Q~0 nop7_q~16 new_n1698 nop7_q~0 $auto$hard_block.cc:122:cell_hard_block$2657.Y[16] +--01 1 +01-- 1 + + +.names $dffe~8^Q~0 new_n1666 new_n1665 $auto$simplemap.cc:248:simplemap_eqne$3524[1] new_n1698 +1-00 0 +-101 0 + + +.names $dffe~8^Q~0 nop7_q~17 new_n1698 nop7_q~1 $auto$hard_block.cc:122:cell_hard_block$2657.Y[17] +--01 1 +01-- 1 + + +.names $dffe~8^Q~0 nop7_q~18 new_n1698 nop7_q~2 $auto$hard_block.cc:122:cell_hard_block$2657.Y[18] +--01 1 +01-- 1 + + +.names $dffe~8^Q~0 nop7_q~19 new_n1698 nop7_q~3 $auto$hard_block.cc:122:cell_hard_block$2657.Y[19] +--01 1 +01-- 1 + + +.names $dffe~8^Q~0 nop7_q~20 new_n1698 nop7_q~4 $auto$hard_block.cc:122:cell_hard_block$2657.Y[20] +--01 1 +01-- 1 + + +.names $dffe~8^Q~0 nop7_q~21 new_n1698 nop7_q~5 $auto$hard_block.cc:122:cell_hard_block$2657.Y[21] +--01 1 +01-- 1 + + +.names $dffe~8^Q~0 nop7_q~22 new_n1698 nop7_q~6 $auto$hard_block.cc:122:cell_hard_block$2657.Y[22] +--01 1 +01-- 1 + + +.names $dffe~8^Q~0 nop7_q~23 new_n1698 nop7_q~7 $auto$hard_block.cc:122:cell_hard_block$2657.Y[23] +--01 1 +01-- 1 + + +.names new_n1709 nop7_q~8 new_n1707 $auto$hard_block.cc:122:cell_hard_block$2657.Y[24] +--0 1 +11- 1 + + +.names nop7_q~0 new_n1708 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~24 $dffe~8^Q~0 new_n1707 +---10 0 +111-- 0 + + +.names new_n1665 new_n1666 new_n1708 +00 1 + + +.names new_n1665 $auto$simplemap.cc:248:simplemap_eqne$3524[1] $dffe~8^Q~0 new_n1709 +001 1 + + +.names new_n1709 nop7_q~9 new_n1711 $auto$hard_block.cc:122:cell_hard_block$2657.Y[25] +--0 1 +11- 1 + + +.names nop7_q~1 new_n1708 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~25 $dffe~8^Q~0 new_n1711 +---10 0 +111-- 0 + + +.names new_n1709 nop7_q~10 new_n1713 $auto$hard_block.cc:122:cell_hard_block$2657.Y[26] +--0 1 +11- 1 + + +.names nop7_q~2 new_n1708 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~26 $dffe~8^Q~0 new_n1713 +---10 0 +111-- 0 + + +.names new_n1709 nop7_q~11 new_n1715 $auto$hard_block.cc:122:cell_hard_block$2657.Y[27] +--0 1 +11- 1 + + +.names nop7_q~3 new_n1708 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~27 $dffe~8^Q~0 new_n1715 +---10 0 +111-- 0 + + +.names new_n1709 nop7_q~12 new_n1717 $auto$hard_block.cc:122:cell_hard_block$2657.Y[28] +--0 1 +11- 1 + + +.names nop7_q~4 new_n1708 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~28 $dffe~8^Q~0 new_n1717 +---10 0 +111-- 0 + + +.names new_n1709 nop7_q~13 new_n1719 $auto$hard_block.cc:122:cell_hard_block$2657.Y[29] +--0 1 +11- 1 + + +.names nop7_q~5 new_n1708 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~29 $dffe~8^Q~0 new_n1719 +---10 0 +111-- 0 + + +.names new_n1709 nop7_q~14 new_n1721 $auto$hard_block.cc:122:cell_hard_block$2657.Y[30] +--0 1 +11- 1 + + +.names nop7_q~6 new_n1708 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~30 $dffe~8^Q~0 new_n1721 +---10 0 +111-- 0 + + +.names new_n1709 nop7_q~15 new_n1723 $auto$hard_block.cc:122:cell_hard_block$2657.Y[31] +--0 1 +11- 1 + + +.names nop7_q~7 new_n1708 $auto$simplemap.cc:248:simplemap_eqne$3524[1] nop7_q~31 $dffe~8^Q~0 new_n1723 +---10 0 +111-- 0 + + +.names new_n1725 new_n1735 new_n1727 new_n1734 $mux~605^Y~0 +--00 1 +01-0 1 + + +.names new_n1651 new_n1653 new_n1652 new_n1654_1 new_n1574 new_n1726 new_n1725 +-1-100 1 +1--100 1 +-10-00 1 +1-0-00 1 +--01-0 1 + + +.names lo110 new_n1523 $dffe~10^Q~0 $dff~81^Q~1 nop7_q~31 new_n1726 +-0011 1 +1-111 1 + + +.names $dff~84^Q~5 new_n1728 $dff~84^Q~3 new_n1727 +--1 0 +01- 0 + + +.names new_n1729 $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1492 new_n1597 \ + $auto$simplemap.cc:248:simplemap_eqne$4611[1] $dff~84^Q~1 new_n1728 +1----0 1 +--0001 1 +-1-001 1 +-10-01 1 +-01011 1 +-00111 1 +-11111 1 + + +.names $sdff~476^Q~0 $sdff~476^Q~8 new_n1733 new_n1730 $dff~84^Q~6 new_n1729 +--0-0 1 +1--01 1 +-1-11 1 + + +.names lo181 lo184 new_n1732 new_n1731 new_n1730 +---0 0 +001- 0 + + +.names new_n1547 new_n1524_1 $dff~80^Q~1 new_n1546 $sdffce~11^Q~0 new_n1731 +----0 0 +1111- 0 + + +.names $dff~80^Q~1 $dff~80^Q~2 lo182 lo183 lo185 new_n1732 +00000 1 + + +.names $sdffe~13^Q~0 $sdffe~12^Q~0 single_port_ram^MEM~0-0^out~0 $dff~84^Q~4 $dff~84^Q~2 new_n1733 +0--00 1 +-0-10 1 +--0-1 1 + + +.names new_n1666 $dff~84^Q~3 new_n1734 +01 1 + + +.names lo110 new_n1523 $dff~81^Q~1 nop7_q~31 $dffe~10^Q~0 $dff~84^Q~5 new_n1735 +-0--01 1 +1---11 1 +--11-1 1 + + +.names new_n1737 $dff~84^Q~5 new_n1665 $dff~84^Q~3 $mux~605^Y~1 +00-0 1 +--11 1 + + +.names new_n1738 $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1524_1 new_n1596 \ + $auto$simplemap.cc:248:simplemap_eqne$4611[1] $dff~84^Q~1 new_n1737 +0----0 0 +--0001 0 +-1-001 0 +-10-01 0 +-01011 0 +-00111 0 +-11111 0 + + +.names $sdff~476^Q~1 $sdff~476^Q~9 new_n1739 new_n1730 $dff~84^Q~6 new_n1738 +--1-0 1 +0--01 1 +-0-11 1 + + +.names $sdffe~13^Q~1 $sdffe~12^Q~1 single_port_ram^MEM~0-1^out~0 $dff~84^Q~4 $dff~84^Q~2 new_n1739 +0--00 1 +-0-10 1 +--0-1 1 + + +.names new_n1741 $dff~84^Q~5 $xor~273^Y~0 $dff~84^Q~3 $mux~605^Y~2 +00-0 1 +--11 1 + + +.names new_n1742 $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1593 new_n1512 \ + $auto$simplemap.cc:248:simplemap_eqne$4611[1] $dff~84^Q~1 new_n1741 +0----0 0 +--0001 0 +-1-001 0 +-10-01 0 +-01011 0 +-00111 0 +-11111 0 + + +.names $sdff~476^Q~2 $sdff~476^Q~10 new_n1743 new_n1730 $dff~84^Q~6 new_n1742 +--1-0 1 +0--01 1 +-0-11 1 + + +.names $sdffe~13^Q~2 $sdffe~12^Q~2 single_port_ram^MEM~0-2^out~0 $dff~84^Q~4 $dff~84^Q~2 new_n1743 +0--00 1 +-0-10 1 +--0-1 1 + + +.names new_n1745 $dff~84^Q~5 $xor~350^Y~0 $dff~84^Q~3 $mux~605^Y~3 +00-0 1 +--11 1 + + +.names new_n1746 $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1591 new_n1525_1 \ + $auto$simplemap.cc:248:simplemap_eqne$4611[1] $dff~84^Q~1 new_n1745 +0----0 0 +--0001 0 +-1-001 0 +-10-01 0 +-01011 0 +-00111 0 +-11111 0 + + +.names $sdff~476^Q~3 $sdff~476^Q~11 new_n1747 new_n1730 $dff~84^Q~6 new_n1746 +--1-0 1 +0--01 1 +-0-11 1 + + +.names $sdffe~13^Q~3 $sdffe~12^Q~3 single_port_ram^MEM~0-3^out~0 $dff~84^Q~4 $dff~84^Q~2 new_n1747 +0--00 1 +-0-10 1 +--0-1 1 + + +.names new_n1749 $dff~84^Q~5 $xor~371^Y~0 $dff~84^Q~3 $mux~605^Y~4 +00-0 1 +--11 1 + + +.names new_n1750 $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1513 new_n1590 \ + $auto$simplemap.cc:248:simplemap_eqne$4611[1] $dff~84^Q~1 new_n1749 +1----0 0 +--0001 0 +-1-001 0 +-10-01 0 +-01011 0 +-00111 0 +-11111 0 + + +.names $sdff~476^Q~4 $sdff~476^Q~12 new_n1751 new_n1730 $dff~84^Q~6 new_n1750 +--0-0 1 +1--01 1 +-1-11 1 + + +.names $sdffe~13^Q~4 $sdffe~12^Q~4 single_port_ram^MEM~0-4^out~0 $dff~84^Q~4 $dff~84^Q~2 new_n1751 +0--00 1 +-0-10 1 +--0-1 1 + + +.names new_n1753 $dff~84^Q~5 $xor~378^Y~0 $dff~84^Q~3 $mux~605^Y~5 +00-0 1 +--11 1 + + +.names new_n1754 $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1586 new_n1515_1 \ + $auto$simplemap.cc:248:simplemap_eqne$4611[1] $dff~84^Q~1 new_n1753 +0----0 0 +--0001 0 +-1-001 0 +-10-01 0 +-01011 0 +-00111 0 +-11111 0 + + +.names $sdff~476^Q~5 $sdff~476^Q~13 new_n1755 new_n1730 $dff~84^Q~6 new_n1754 +--1-0 1 +0--01 1 +-0-11 1 + + +.names $sdffe~13^Q~5 $sdffe~12^Q~5 single_port_ram^MEM~0-5^out~0 $dff~84^Q~4 $dff~84^Q~2 new_n1755 +0--00 1 +-0-10 1 +--0-1 1 + + +.names new_n1757 $dff~84^Q~5 $xor~385^Y~0 $dff~84^Q~3 $mux~605^Y~6 +00-0 1 +--11 1 + + +.names new_n1758 $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1598 new_n1520_1 \ + $auto$simplemap.cc:248:simplemap_eqne$4611[1] $dff~84^Q~1 new_n1757 +0----0 0 +--0001 0 +-1-001 0 +-10-01 0 +-01011 0 +-00111 0 +-11111 0 + + +.names $sdff~476^Q~6 $sdff~476^Q~14 new_n1759 new_n1730 $dff~84^Q~6 new_n1758 +--1-0 1 +0--01 1 +-0-11 1 + + +.names $sdffe~13^Q~6 $sdffe~12^Q~6 single_port_ram^MEM~0-6^out~0 $dff~84^Q~4 $dff~84^Q~2 new_n1759 +0--00 1 +-0-10 1 +--0-1 1 + + +.names new_n1761 $dff~84^Q~5 $xor~392^Y~0 $dff~84^Q~3 $mux~605^Y~7 +00-0 1 +--11 1 + + +.names new_n1762 $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1605_1 new_n1528 \ + $auto$simplemap.cc:248:simplemap_eqne$4611[1] $dff~84^Q~1 new_n1761 +0----0 0 +--0001 0 +-1-001 0 +-10-01 0 +-01011 0 +-00111 0 +-11111 0 + + +.names $sdff~476^Q~7 $sdff~476^Q~15 new_n1763 new_n1730 $dff~84^Q~6 new_n1762 +--1-0 1 +0--01 1 +-0-11 1 + + +.names $sdffe~13^Q~7 $sdffe~12^Q~7 single_port_ram^MEM~0-7^out~0 $dff~84^Q~4 $dff~84^Q~2 new_n1763 +0--00 1 +-0-10 1 +--0-1 1 + + +.names new_n1657 single_port_ram^MEM~0-8^out~0 new_n1765 $xor~399^Y~0 $dff~84^Q~5 $dff~84^Q~3 $mux~605^Y~8 +--1-00 1 +11--00 1 +---1-1 1 + + +.names $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1603 new_n1516 $auto$simplemap.cc:248:simplemap_eqne$4611[1] \ + $dff~84^Q~1 new_n1765 +-0001 1 +1-001 1 +10-01 1 +01011 1 +00111 1 +11111 1 + + +.names new_n1657 single_port_ram^MEM~0-9^out~0 new_n1767 $xor~406^Y~0 $dff~84^Q~5 $dff~84^Q~3 $mux~605^Y~9 +--1-00 1 +11--00 1 +---1-1 1 + + +.names $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1602 new_n1519_1 $auto$simplemap.cc:248:simplemap_eqne$4611[1] \ + $dff~84^Q~1 new_n1767 +-0001 1 +1-001 1 +10-01 1 +01011 1 +00111 1 +11111 1 + + +.names new_n1657 single_port_ram^MEM~0-10^out~0 new_n1769 $xor~203^Y~0 $dff~84^Q~5 $dff~84^Q~3 $mux~605^Y~10 +--1-00 1 +11--00 1 +---1-1 1 + + +.names $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1610_1 new_n1507 $auto$simplemap.cc:248:simplemap_eqne$4611[1] \ + $dff~84^Q~1 new_n1769 +-0001 1 +1-001 1 +10-01 1 +01011 1 +00111 1 +11111 1 + + +.names new_n1772 new_n1771 new_n1608 new_n1609_1 $dff~84^Q~3 $mux~605^Y~11 +-0001 1 +-1101 1 +-1011 1 +-0111 1 +1---- 1 + + +.names new_n1680 new_n1610_1 new_n1611 new_n1771 +-11 1 +1-1 1 +11- 1 + + +.names new_n1657 single_port_ram^MEM~0-11^out~0 new_n1773 new_n1658 new_n1772 +--11 1 +11-1 1 + + +.names $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1608 new_n1535 $auto$simplemap.cc:248:simplemap_eqne$4611[1] \ + $dff~84^Q~1 new_n1773 +-0001 1 +1-001 1 +10-01 1 +01011 1 +00111 1 +11111 1 + + +.names new_n1775 new_n1582 new_n1616 new_n1617 $dff~84^Q~3 $mux~605^Y~12 +-0001 1 +-1101 1 +-1011 1 +-0111 1 +1---- 1 + + +.names new_n1657 single_port_ram^MEM~0-12^out~0 new_n1776 new_n1658 new_n1775 +--11 1 +11-1 1 + + +.names $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1616 new_n1527 $auto$simplemap.cc:248:simplemap_eqne$4611[1] \ + $dff~84^Q~1 new_n1776 +-0001 1 +1-001 1 +10-01 1 +01011 1 +00111 1 +11111 1 + + +.names new_n1779 new_n1778 new_n1614_1 new_n1615_1 $dff~84^Q~3 $mux~605^Y~13 +-0001 1 +-1101 1 +-1011 1 +-0111 1 +1---- 1 + + +.names new_n1582 new_n1616 new_n1617 new_n1778 +-11 1 +1-1 1 +11- 1 + + +.names new_n1657 single_port_ram^MEM~0-13^out~0 new_n1780 new_n1658 new_n1779 +--11 1 +11-1 1 + + +.names $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1614_1 new_n1537 $auto$simplemap.cc:248:simplemap_eqne$4611[1] \ + $dff~84^Q~1 new_n1780 +-0001 1 +1-001 1 +10-01 1 +01011 1 +00111 1 +11111 1 + + +.names new_n1657 single_port_ram^MEM~0-14^out~0 new_n1783 new_n1782 new_n1658 $mux~605^Y~14 +--1-1 1 +11--1 1 +---1- 1 + + +.names new_n1778 new_n1618 new_n1612 new_n1614_1 new_n1615_1 $dff~84^Q~3 new_n1782 +--1001 1 +-1-001 1 +0-1-01 1 +01--01 1 +-00111 1 +100-11 1 +0-10-1 1 +01-0-1 1 +1001-1 1 + + +.names $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1613 new_n1536 $auto$simplemap.cc:248:simplemap_eqne$4611[1] \ + $dff~84^Q~1 new_n1783 +-0001 1 +1-001 1 +10-01 1 +01011 1 +00111 1 +11111 1 + + +.names new_n1786 new_n1785 new_n1620_1 new_n1621 $dff~84^Q~3 $mux~605^Y~15 +-0001 1 +-1101 1 +-1011 1 +-0111 1 +1---- 1 + + +.names new_n1581 new_n1618 new_n1785 +00 1 + + +.names new_n1657 single_port_ram^MEM~0-15^out~0 new_n1787 new_n1658 new_n1786 +--11 1 +11-1 1 + + +.names $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1620_1 new_n1511 $auto$simplemap.cc:248:simplemap_eqne$4611[1] \ + $dff~84^Q~1 new_n1787 +-0001 1 +1-001 1 +10-01 1 +01011 1 +00111 1 +11111 1 + + +.names new_n1790 new_n1789 new_n1619_1 new_n1622 $dff~84^Q~3 $mux~605^Y~16 +-1001 1 +-0101 1 +-0011 1 +-1111 1 +1---- 1 + + +.names new_n1785 new_n1620_1 new_n1621 new_n1789 +-11 1 +1-1 1 +11- 1 + + +.names new_n1657 single_port_ram^MEM~0-16^out~0 new_n1791 new_n1658 new_n1790 +--11 1 +11-1 1 + + +.names new_n1619_1 $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1506 $auto$simplemap.cc:248:simplemap_eqne$4611[1] \ + $dff~84^Q~1 new_n1791 +-1001 1 +1-001 1 +11-01 1 +00011 1 +10111 1 +01111 1 + + +.names new_n1793 new_n1580 new_n1624 new_n1625 $dff~84^Q~3 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$auto$simplemap.cc:248:simplemap_eqne$4422[2] $auto$simplemap.cc:248:simplemap_eqne$4422[3] new_n1937 +11111 1 + + +.names $sdff~432^Q~0 $dffe~8^Q~3 resetn n699 +001 1 + + +.names n794 $dffe~3^Q~0 new_n1940 n704 +1-0 1 +-11 1 + + +.names $auto$simplemap.cc:248:simplemap_eqne$4422[3] $auto$simplemap.cc:248:simplemap_eqne$4422[2] new_n1907 new_n1941 \ + new_n1940 +---1 0 +011- 0 + + +.names $auto$simplemap.cc:248:simplemap_eqne$4492[1] $auto$simplemap.cc:248:simplemap_eqne$4422[2] \ + $auto$simplemap.cc:248:simplemap_eqne$4422[3] $auto$simplemap.cc:248:simplemap_eqne$4422[0] new_n1907 new_n1941 +00011 1 + + +.names lo011 dual_port_ram^MEM~3-15^out1~0 n794 resetn li011 +1-01 1 +-111 1 + + +.names $sdffe~483^Q~20 dual_port_ram^MEM~3-20^out1~0 n794 resetn n714 +1-01 1 +-111 1 + + +.names $sdffe~483^Q~21 dual_port_ram^MEM~3-21^out1~0 n794 resetn n719 +1-01 1 +-111 1 + + +.names $sdffe~483^Q~22 dual_port_ram^MEM~3-22^out1~0 n794 resetn n724 +1-01 1 +-111 1 + + +.names $sdffe~483^Q~23 dual_port_ram^MEM~3-23^out1~0 n794 resetn n729 +1-01 1 +-111 1 + + +.names $sdffe~483^Q~24 dual_port_ram^MEM~3-24^out1~0 n794 resetn n734 +1-01 1 +-111 1 + + +.names $sdffe~483^Q~25 dual_port_ram^MEM~3-25^out1~0 n794 resetn n739 +1-01 1 +-111 1 + + +.names lo175 new_n1921 new_n1908 $auto$simplemap.cc:248:simplemap_eqne$3403[0] new_n1922 \ + $auto$simplemap.cc:248:simplemap_eqne$4422[0] n744 +----01 1 +-0-11- 1 +-101-- 1 +111--- 1 + + +.names lo176 new_n1921 new_n1908 $auto$simplemap.cc:248:simplemap_eqne$4611[1] new_n1922 \ + $auto$simplemap.cc:248:simplemap_eqne$4492[1] n749 +----01 1 +-0-11- 1 +-101-- 1 +111--- 1 + + +.names $auto$simplemap.cc:248:simplemap_eqne$4422[0] $dffe~8^Q~0 $auto$simplemap.cc:248:simplemap_eqne$4422[2] \ + $auto$simplemap.cc:248:simplemap_eqne$4422[3] new_n1925 $auto$simplemap.cc:248:simplemap_eqne$4492[1] n754 +1-0011 0 +1-1111 0 +-0---1 0 +-0--0- 0 +-001-- 0 + + +.names $auto$simplemap.cc:248:simplemap_eqne$4422[0] new_n1925 $auto$simplemap.cc:248:simplemap_eqne$4422[3] \ + $auto$simplemap.cc:248:simplemap_eqne$4422[2] $auto$simplemap.cc:248:simplemap_eqne$4492[1] \ + $auto$simplemap.cc:248:simplemap_eqne$3524[1] n759 +--0111 1 +--10-1 1 +-0---1 1 +0----1 1 +01-10- 1 +010-0- 1 + + +.names $auto$simplemap.cc:248:simplemap_eqne$4492[1] new_n1925 $auto$simplemap.cc:248:simplemap_eqne$4422[0] \ + $auto$simplemap.cc:248:simplemap_eqne$4422[3] $auto$simplemap.cc:248:simplemap_eqne$4422[2] $dffe~8^Q~3 n764 +---101 1 +1---11 1 +1-0--1 1 +-0---1 1 +-1111- 1 + + +.names new_n1957 resetn li023 +01 1 + + +.names dual_port_ram^MEM~3-11^out1~0 $dff~82^Q~1 dual_port_ram^MEM~3-16^out1~0 lo023 $dff~82^Q~0 n794 new_n1957 +---0-0 1 +01--01 1 +--0-11 1 + + +.names new_n1959 resetn li024 +01 1 + + +.names dual_port_ram^MEM~3-12^out1~0 $dff~82^Q~1 dual_port_ram^MEM~3-17^out1~0 lo024 $dff~82^Q~0 n794 new_n1959 +---0-0 1 +01--01 1 +--0-11 1 + + +.names new_n1961 resetn li025 +01 1 + + +.names dual_port_ram^MEM~3-13^out1~0 $dff~82^Q~1 dual_port_ram^MEM~3-18^out1~0 lo025 $dff~82^Q~0 n794 new_n1961 +---0-0 1 +01--01 1 +--0-11 1 + + +.names new_n1963 resetn li026 +01 1 + + +.names dual_port_ram^MEM~3-14^out1~0 $dff~82^Q~1 dual_port_ram^MEM~3-19^out1~0 lo026 $dff~82^Q~0 n794 new_n1963 +---0-0 1 +01--01 1 +--0-11 1 + + +.names new_n1965 resetn li027 +01 1 + + +.names dual_port_ram^MEM~3-15^out1~0 $dff~82^Q~1 dual_port_ram^MEM~3-20^out1~0 lo027 $dff~82^Q~0 n794 new_n1965 +---0-0 1 +01--01 1 +--0-11 1 + + +.names $dffe~9^Q~0 new_n1661 $sdff~479^Q~0 resetn n799 +-001 1 +1-01 1 + + +.names new_n1968 $dff~82^Q~0 new_n1971 n804 +--0 1 +01- 1 + + +.names dual_port_ram^MEM~3-0^out1~0 dual_port_ram^MEM~3-3^out1~0 dual_port_ram^MEM~3-5^out1~0 dual_port_ram^MEM~3-2^out1~0 \ + dual_port_ram^MEM~3-1^out1~0 new_n1969 new_n1968 +--1011 1 +1-0111 1 +-0---1 1 + + +.names dual_port_ram^MEM~3-2^out1~0 dual_port_ram^MEM~3-1^out1~0 dual_port_ram^MEM~3-0^out1~0 dual_port_ram^MEM~3-5^out1~0 \ + dual_port_ram^MEM~3-4^out1~0 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$dffe~447^Q~16 +1 1 + + +.names lo098 $dffe~447^Q~17 +1 1 + + +.names lo099 $dffe~447^Q~18 +1 1 + + +.names lo100 $dffe~447^Q~19 +1 1 + + +.names lo101 $dffe~447^Q~20 +1 1 + + +.names lo102 $dffe~447^Q~21 +1 1 + + +.names lo103 $dffe~447^Q~22 +1 1 + + +.names lo104 $dffe~447^Q~23 +1 1 + + +.names lo105 $dffe~447^Q~24 +1 1 + + +.names lo106 $dffe~447^Q~25 +1 1 + + +.names lo107 $dffe~447^Q~26 +1 1 + + +.names lo108 $dffe~447^Q~27 +1 1 + + +.names lo109 $dffe~447^Q~28 +1 1 + + +.names lo110 $dffe~447^Q~29 +1 1 + + +.names lo023 $sdffe~491^Q~0 +1 1 + + +.names lo024 $sdffe~491^Q~1 +1 1 + + +.names lo025 $sdffe~491^Q~2 +1 1 + + +.names lo026 $sdffe~491^Q~3 +1 1 + + +.names lo027 $sdffe~491^Q~4 +1 1 + + + +.end + + + + +.model adder + + +.inputs cin b a + + +.outputs sumout cout + + +.blackbox + + + +.end + + + + +.model dual_port_ram + + +.inputs clk we1 we2 addr2[0] addr2[1] addr2[2] addr2[3] addr2[4] addr2[5] addr2[6] addr2[7] addr2[8] addr2[9] addr2[10] \ + addr2[11] addr2[12] addr2[13] addr2[14] data1 data2 addr1[0] addr1[1] addr1[2] addr1[3] addr1[4] addr1[5] addr1[6] addr1[7] \ + addr1[8] addr1[9] addr1[10] addr1[11] addr1[12] addr1[13] addr1[14] + + +.outputs out2 out1 + + +.blackbox + + + +.end + + + + +.model multiply + + +.inputs b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] \ + b[21] b[22] b[23] b[24] b[25] b[26] b[27] b[28] b[29] b[30] b[31] b[32] b[33] b[34] b[35] a[0] a[1] a[2] a[3] a[4] a[5] a[6] \ + a[7] a[8] a[9] a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] a[21] a[22] a[23] a[24] a[25] a[26] a[27] \ + a[28] a[29] a[30] a[31] a[32] a[33] a[34] a[35] + + +.outputs out[0] out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] out[10] out[11] out[12] out[13] out[14] \ + out[15] out[16] out[17] out[18] out[19] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] \ + out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[38] out[39] out[40] out[41] out[42] out[43] out[44] \ + out[45] out[46] out[47] out[48] out[49] out[50] out[51] out[52] out[53] out[54] out[55] out[56] out[57] out[58] out[59] \ + out[60] out[61] out[62] out[63] out[64] out[65] out[66] out[67] out[68] out[69] out[70] out[71] + + +.blackbox + + + +.end + + + + +.model single_port_ram + + +.inputs clk data we addr[0] addr[1] addr[2] addr[3] addr[4] addr[5] addr[6] addr[7] addr[8] addr[9] addr[10] addr[11] \ + addr[12] addr[13] addr[14] + + +.outputs out + + +.blackbox + + + +.end + + + + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/constraints/spree.fplace b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/constraints/spree.fplace new file mode 100644 index 00000000000..c5967649e73 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/constraints/spree.fplace @@ -0,0 +1,1167 @@ +# Flat Placement File +# Auto-generated by VPR 9.0.0-dev+v8.0.0-13697-g4ea6b570aa-dirty +# Created: 2025-08-25T20:29:05 +# +# This file prints the following information for each atom in the netlist: +# # + +$add~482^ADD~4-19[1] 13 11 0 0 #0 adder +$add~482^ADD~4-18[1] 13 11 0 0 #0 adder +$add~482^ADD~4-17[1] 13 11 0 0 #0 adder +$add~482^ADD~4-16[1] 13 11 0 0 #0 adder +$add~482^ADD~4-15[1] 13 11 0 0 #0 adder +$add~482^ADD~4-14[1] 13 11 0 0 #0 adder +$add~482^ADD~4-1[1] 13 11 0 0 #0 adder +$add~482^ADD~4-2[1] 13 11 0 0 #0 adder +$add~482^ADD~4-0~dummy_output~0~1 13 11 0 0 #0 adder +$add~482^ADD~4-3[1] 13 11 0 0 #0 adder +$add~482^ADD~4-4[1] 13 11 0 0 #0 adder +$add~482^ADD~4-5[1] 13 11 0 0 #0 adder +$add~482^ADD~4-6[1] 13 11 0 0 #0 adder +$add~482^ADD~4-7[1] 13 11 0 0 #0 adder +$add~482^ADD~4-8[1] 13 11 0 0 #0 adder +$add~482^ADD~4-9[1] 13 11 0 0 #0 adder +$add~482^ADD~4-10[1] 13 11 0 0 #0 adder +$add~482^ADD~4-11[1] 13 11 0 0 #0 adder +$add~482^ADD~4-12[1] 13 11 0 0 #0 adder +$add~482^ADD~4-13[1] 13 11 0 0 #0 adder +$mul~477[0] 6 13 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10 0 0 0 #98 inpad +boot_iaddr~0 11 0 0 0 #99 inpad +boot_iaddr~1 12 0 0 0 #100 inpad +clk 0 1 0 0 #101 inpad +resetn 12 19 0 2 #102 inpad +boot_idata~12 10 0 0 1 #103 inpad +boot_iwe 10 19 0 1 #104 inpad +boot_idata~31 11 0 0 1 #105 inpad +boot_idata~30 12 0 0 1 #106 inpad +boot_idata~29 9 0 0 0 #107 inpad +boot_iaddr~8 10 19 0 2 #108 inpad +boot_idata~28 9 0 0 1 #109 inpad +boot_idata~11 9 0 0 2 #110 inpad +boot_idata~27 10 0 0 2 #111 inpad +boot_idata~26 10 0 0 3 #112 inpad +boot_iaddr~7 11 0 0 2 #113 inpad +boot_iaddr~6 11 0 0 3 #114 inpad +boot_idata~25 10 19 0 3 #115 inpad +boot_iaddr~9 10 0 0 4 #116 inpad +boot_idata~10 11 0 0 4 #117 inpad +boot_iaddr~2 9 0 0 3 #118 inpad +boot_idata~24 12 0 0 2 #119 inpad +boot_idata~17 11 0 0 5 #120 inpad +boot_idata~23 8 0 0 0 #121 inpad +boot_idata~22 10 0 0 5 #122 inpad +boot_idata~21 9 0 0 4 #123 inpad +boot_iaddr~5 12 0 0 3 #124 inpad +boot_iaddr~4 11 0 0 6 #125 inpad +boot_idata~13 10 19 0 4 #126 inpad +boot_idata~20 9 0 0 5 #127 inpad +boot_iaddr~3 10 0 0 6 #128 inpad +boot_idata~18 12 0 0 4 #129 inpad +boot_idata~14 8 0 0 1 #130 inpad +boot_idata~15 8 0 0 2 #131 inpad +boot_idata~0 10 0 0 7 #132 inpad +boot_idata~1 10 19 0 5 #133 inpad +boot_idata~2 8 0 0 3 #134 inpad +boot_idata~3 12 0 0 5 #135 inpad +boot_idata~4 9 0 0 6 #136 inpad +boot_idata~5 11 0 0 7 #137 inpad +boot_idata~6 9 0 0 7 #138 inpad +boot_idata~7 10 19 0 6 #139 inpad +boot_idata~8 10 19 0 7 #140 inpad +boot_idata~9 12 0 0 6 #141 inpad diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/task_list.txt index a0323c82570..16b7619af7f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/task_list.txt @@ -2,3 +2,4 @@ regression_tests/vtr_reg_basic_odin/basic_no_timing regression_tests/vtr_reg_basic_odin/basic_timing regression_tests/vtr_reg_basic_odin/basic_timing_no_sdc regression_tests/vtr_reg_basic_odin/hdl_include_odin +regression_tests/vtr_reg_basic_odin/basic_flat_recon diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_reconstruction/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_reconstruction/config/config.txt new file mode 100644 index 00000000000..bcbdb93ab6b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_reconstruction/config/config.txt @@ -0,0 +1,47 @@ +############################################## +# Configuration file for running experiments +############################################## + +# NOTE: To run this task, the Flat Placement Files are needed. These files needs to be +# decompressed in order to run. In the root VTR directory, run: +# make get_flat_placements + + +# Path to directory of circuits to use +circuits_dir=benchmarks/titan_blif/titan23/stratixiv + +# Path to directory of SDCs to use +sdc_dir=benchmarks/titan_blif/titan23/stratixiv + +# Path to directory of architectures to use +archs_dir=arch/titan + +# Add circuits to list to sweep +circuit_list_add=neuron_stratixiv_arch_timing.blif +circuit_list_add=cholesky_bdti_stratixiv_arch_timing.blif +circuit_list_add=minres_stratixiv_arch_timing.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(neuron_stratixiv_arch_timing.blif, device=titan_small) +circuit_constraint_list_add=(cholesky_bdti_stratixiv_arch_timing.blif, device=titan_medium) +circuit_constraint_list_add=(minres_stratixiv_arch_timing.blif, device=titan_large) + +# Read flat placement inputs +circuit_constraint_list_add=(neuron_stratixiv_arch_timing.blif, read_flat_place=../../../../../ap_reconstruction/constraints/neuron_stratixiv_arch_timing.fplace) +circuit_constraint_list_add=(cholesky_bdti_stratixiv_arch_timing.blif, read_flat_place=../../../../../ap_reconstruction/constraints/cholesky_bdti_stratixiv_arch_timing.fplace) +circuit_constraint_list_add=(minres_stratixiv_arch_timing.blif, read_flat_place=../../../../../ap_reconstruction/constraints/minres_stratixiv_arch_timing.fplace) + +# Add architectures to list to sweep +arch_list_add=stratixiv_arch.timing.xml + +# Parse info and how to parse +parse_file=vpr_ap_reconstruction.txt + +# How to parse QoR info +qor_parse_file=qor_ap_flatrecon_fl_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_reconstruction.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --route_chan_width 300 --ap_detailed_placer none --ap_full_legalizer flat-recon diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_reconstruction/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_reconstruction/config/golden_results.txt new file mode 100644 index 00000000000..888a4473635 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_reconstruction/config/golden_results.txt @@ -0,0 +1,4 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time post_fl_atom_err post_fl_total_disp post_fl_avg_disp post_fl_max_disp ap_fl_max_rss num_total_clusters +stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 374.52 vpr 3.24 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-13697-g4ea6b570aa-dirty release IPO VTR_ASSERT_LEVEL=1 gprof GNU 11.4.0 on Linux-6.8.0-52-generic x86_64 2025-08-25T20:29:05 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing/vtr_flow/tasks 3398884 42 35 90877 0 1 53545 3981 150 111 16650 -1 titan_small -1 -1 -1 -1 -1 -1 -1 -1 3319.2 MiB 286.81 -1 -1 -1 -1 -1 -1 38.17 -1 -1 -1 -1 3319.2 MiB 286.81 3319.2 MiB 243.90 -1 -1 -1 -1 -1 -1 -1 -1 0.75087 0.673333 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3.561439 8091.000000 0.093134 18.000000 3319.2 3981 +stratixiv_arch.timing.xml cholesky_bdti_stratixiv_arch_timing.blif common 923.04 vpr 7.01 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 94 -1 -1 success v8.0.0-13697-g4ea6b570aa-dirty release IPO VTR_ASSERT_LEVEL=1 gprof GNU 11.4.0 on Linux-6.8.0-52-generic x86_64 2025-08-25T20:29:05 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing/vtr_flow/tasks 7351000 94 68 262204 0 1 169929 12502 225 167 37575 -1 titan_medium -1 -1 -1 -1 -1 -1 -1 -1 7178.7 MiB 734.25 -1 -1 -1 -1 -1 -1 101.09 -1 -1 -1 -1 7178.7 MiB 734.25 7178.7 MiB 619.30 -1 -1 -1 -1 -1 -1 -1 -1 1.88277 1.61981 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3.743180 56483.000000 0.221088 65.000000 7178.7 12502 +stratixiv_arch.timing.xml minres_stratixiv_arch_timing.blif common 1480.97 vpr 9.10 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 129 -1 -1 success v8.0.0-13697-g4ea6b570aa-dirty release IPO VTR_ASSERT_LEVEL=1 gprof GNU 11.4.0 on Linux-6.8.0-52-generic x86_64 2025-08-25T20:29:05 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing/vtr_flow/tasks 9544248 129 100 263048 0 3 187427 10468 300 222 66600 -1 titan_large -1 -1 -1 -1 -1 -1 -1 -1 9320.6 MiB 1167.21 -1 -1 -1 -1 -1 -1 180.02 -1 -1 -1 -1 9320.6 MiB 1167.21 9320.6 MiB 973.17 -1 -1 -1 -1 -1 -1 -1 -1 1.90334 1.65208 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 5.681995 30006.000000 0.116537 14.000000 9320.6 10468 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_reconstruction/constraints/flat_placements.zip b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_reconstruction/constraints/flat_placements.zip new file mode 100644 index 00000000000..b2695aee118 Binary files /dev/null and b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_reconstruction/constraints/flat_placements.zip differ diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt index 474a66e48f4..ad51b1f750c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt @@ -1,4 +1,5 @@ regression_tests/vtr_reg_nightly_test7/ap_titan +regression_tests/vtr_reg_nightly_test7/ap_reconstruction regression_tests/vtr_reg_nightly_test7/titan_other_run_flat regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor #regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_run_flat diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flatrecon_full_legalizer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flatrecon_full_legalizer/config/config.txt new file mode 100644 index 00000000000..4644bf907e9 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flatrecon_full_legalizer/config/config.txt @@ -0,0 +1,52 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flat +# placement reconstruction full legalizer. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=ex5p.pre-vpr.blif +circuit_list_add=frisc.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(ex5p.pre-vpr.blif, device=mcnc_small) +circuit_constraint_list_add=(frisc.pre-vpr.blif, device=mcnc_medium) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(ex5p.pre-vpr.blif, route_chan_width=68) +circuit_constraint_list_add=(frisc.pre-vpr.blif, route_chan_width=96) + +# Read in the flat placement files +circuit_constraint_list_add=(apex4.pre-vpr.blif, read_flat_place=../../../../../flatrecon_full_legalizer/constraints/apex4.fplace) +circuit_constraint_list_add=(ex5p.pre-vpr.blif, read_flat_place=../../../../../flatrecon_full_legalizer/constraints/ex5p.fplace) +circuit_constraint_list_add=(frisc.pre-vpr.blif, read_flat_place=../../../../../flatrecon_full_legalizer/constraints/frisc.fplace) + + +# Parse info and how to parse +parse_file=vpr_ap_reconstruction.txt + +# How to parse QoR info +qor_parse_file=qor_ap_flatrecon_fl_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_reconstruction.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_detailed_placer none --ap_full_legalizer flat-recon + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flatrecon_full_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flatrecon_full_legalizer/config/golden_results.txt new file mode 100644 index 00000000000..53ffe270b8b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flatrecon_full_legalizer/config/golden_results.txt @@ -0,0 +1,4 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time post_fl_atom_err post_fl_total_disp post_fl_avg_disp post_fl_max_disp ap_fl_max_rss num_total_clusters +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 0.82 vpr 77.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-13697-g4ea6b570aa-dirty release IPO VTR_ASSERT_LEVEL=1 gprof GNU 11.4.0 on Linux-6.8.0-52-generic x86_64 2025-08-25T20:29:05 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79340 9 19 896 0 0 545 109 16 16 256 -1 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#159 lut +n2326 8 7 0 0 #159 lut +n3190 8 7 0 0 #159 lut +n3398 8 7 0 0 #159 lut +[16025] 8 7 0 0 #159 ff +n2481 8 7 0 0 #159 lut +[10175] 10 7 0 0 #160 ff +n3596_1 10 7 0 0 #160 lut +[13010] 10 7 0 0 #160 ff +[17362] 10 7 0 0 #160 ff +[6920] 10 7 0 0 #160 ff +n1134 10 7 0 0 #160 lut +n4131 10 7 0 0 #160 lut +n2160 10 7 0 0 #160 lut +[5135] 10 7 0 0 #160 ff +n559 10 7 0 0 #160 lut +n2982 10 7 0 0 #160 lut +n2957 10 7 0 0 #160 lut +n3595 10 7 0 0 #160 lut +n4518 10 7 0 0 #160 lut +n1024 5 3 0 0 #161 lut +n4294 5 3 0 0 #161 lut +n4293 5 3 0 0 #161 lut +[10265] 5 3 0 0 #161 ff +[15635] 5 3 0 0 #161 ff +[6590] 5 3 0 0 #161 ff +n3737 5 3 0 0 #161 lut +n1029 5 3 0 0 #161 lut +[6575] 5 3 0 0 #161 ff +n4257 5 3 0 0 #161 lut +[7295] 5 3 0 0 #161 ff +n3802 5 3 0 0 #161 lut +n2188 5 3 0 0 #161 lut +n3738 5 3 0 0 #161 lut +n4076_1 5 3 0 0 #161 lut +n1251 5 3 0 0 #161 lut +n4292 5 3 0 0 #161 lut +n4362 7 14 0 0 #162 lut +n1563 7 14 0 0 #162 lut +n3192 7 14 0 0 #162 lut +n2466 7 14 0 0 #162 lut +n3876 7 14 0 0 #162 lut +n3122 7 14 0 0 #162 lut +[8285] 7 14 0 0 #162 ff +[11210] 7 14 0 0 #162 ff +n4487 7 6 0 0 #163 lut +n1291 9 6 0 0 #164 lut +n3721 9 6 0 0 #164 lut +[7415] 9 6 0 0 #164 ff +[15380] 9 6 0 0 #164 ff +n1498 9 1 0 0 #165 lut +n3943 9 1 0 0 #165 lut +[8075] 9 1 0 0 #165 ff +[16085] 9 1 0 0 #165 ff +n4061 14 6 0 0 #166 lut +n3061 14 6 0 0 #166 lut +n2983 14 6 0 0 #166 lut +[17180] 14 6 0 0 #166 ff +n3833 3 11 0 0 #167 lut +n1104 3 11 0 0 #167 lut +n3665 3 11 0 0 #167 lut +n408 3 11 0 0 #167 lut +n3713 3 11 0 0 #167 lut +[6830] 3 11 0 0 #167 ff +[4655] 3 11 0 0 #167 ff +n1655 1 1 0 0 #168 lut +n3655 1 1 0 0 #168 lut +[8570] 1 1 0 0 #168 ff +n4262 7 10 0 0 #169 lut +n4217 7 10 0 0 #169 lut +n3709 7 10 0 0 #169 lut +n3286 7 10 0 0 #169 lut +n3757 1 6 0 0 #170 lut +n3082 1 6 0 0 #170 lut +n3775 10 1 0 0 #171 lut +n4378 10 1 0 0 #171 lut +[18038] 10 1 0 0 #171 ff +n4051_1 10 12 0 0 #172 lut +out:paddress_0_0_ 8 15 0 0 #173 outpad +out:paddress_10_10_ 3 0 0 0 #174 outpad +out:paddress_11_11_ 4 15 0 0 #175 outpad +out:paddress_12_12_ 5 15 0 0 #176 outpad +out:paddress_13_13_ 4 15 0 1 #177 outpad +out:paddress_14_14_ 8 15 0 1 #178 outpad +out:paddress_15_15_ 5 0 0 0 #179 outpad +out:paddress_1_1_ 11 0 0 0 #180 outpad +out:paddress_2_2_ 9 15 0 0 #181 outpad +out:paddress_3_3_ 12 0 0 0 #182 outpad +out:paddress_4_4_ 5 0 0 1 #183 outpad +out:paddress_5_5_ 11 15 0 0 #184 outpad +out:paddress_6_6_ 7 0 0 0 #185 outpad +out:paddress_7_7_ 4 15 0 2 #186 outpad +out:paddress_8_8_ 3 0 0 1 #187 outpad +out:paddress_9_9_ 4 0 0 0 #188 outpad +out:pdata_0_0_ 12 0 0 1 #189 outpad +out:pdata_10_10_ 2 0 0 0 #190 outpad +out:pdata_11_11_ 4 15 0 3 #191 outpad +out:pdata_12_12_ 3 0 0 2 #192 outpad +out:pdata_13_13_ 8 0 0 0 #193 outpad +out:pdata_14_14_ 5 15 0 1 #194 outpad +out:pdata_15_15_ 5 0 0 2 #195 outpad +out:pdata_1_1_ 12 15 0 0 #196 outpad +out:pdata_2_2_ 11 15 0 1 #197 outpad +out:pdata_3_3_ 12 0 0 2 #198 outpad +out:pdata_4_4_ 13 0 0 0 #199 outpad +out:pdata_5_5_ 10 15 0 0 #200 outpad +out:pdata_6_6_ 5 0 0 3 #201 outpad +out:pdata_7_7_ 6 0 0 0 #202 outpad +out:pdata_8_8_ 7 0 0 1 #203 outpad +out:pdata_9_9_ 5 0 0 4 #204 outpad +out:pdn 10 0 0 0 #205 outpad +out:piack_0_0_ 6 0 0 1 #206 outpad +out:ppeaka_0_0_ 11 0 0 1 #207 outpad +out:ppeaka_10_10_ 1 0 0 0 #208 outpad +out:ppeaka_11_11_ 1 0 0 1 #209 outpad +out:ppeaka_12_12_ 5 15 0 2 #210 outpad +out:ppeaka_13_13_ 6 0 0 2 #211 outpad +out:ppeaka_14_14_ 5 15 0 3 #212 outpad +out:ppeaka_15_15_ 10 0 0 1 #213 outpad +out:ppeaka_1_1_ 10 0 0 2 #214 outpad +out:ppeaka_2_2_ 11 15 0 2 #215 outpad +out:ppeaka_3_3_ 15 8 0 0 #216 outpad +out:ppeaka_4_4_ 14 0 0 0 #217 outpad +out:ppeaka_5_5_ 5 15 0 4 #218 outpad +out:ppeaka_6_6_ 7 0 0 2 #219 outpad +out:ppeaka_7_7_ 3 0 0 3 #220 outpad +out:ppeaka_8_8_ 0 6 0 0 #221 outpad +out:ppeaka_9_9_ 4 0 0 1 #222 outpad +out:ppeakb_0_0_ 10 0 0 3 #223 outpad +out:ppeakb_10_10_ 4 0 0 2 #224 outpad +out:ppeakb_11_11_ 4 0 0 3 #225 outpad +out:ppeakb_12_12_ 4 0 0 4 #226 outpad +out:ppeakb_13_13_ 4 0 0 5 #227 outpad +out:ppeakb_14_14_ 5 0 0 5 #228 outpad +out:ppeakb_15_15_ 11 0 0 2 #229 outpad +out:ppeakb_1_1_ 13 0 0 1 #230 outpad +out:ppeakb_2_2_ 11 0 0 3 #231 outpad +out:ppeakb_3_3_ 7 0 0 3 #232 outpad +out:ppeakb_4_4_ 11 0 0 4 #233 outpad +out:ppeakb_5_5_ 11 0 0 5 #234 outpad +out:ppeakb_6_6_ 8 0 0 1 #235 outpad +out:ppeakb_7_7_ 9 0 0 0 #236 outpad +out:ppeakb_8_8_ 0 6 0 1 #237 outpad +out:ppeakb_9_9_ 2 0 0 1 #238 outpad +out:ppeaki_0_0_ 7 0 0 4 #239 outpad +out:ppeaki_10_10_ 10 0 0 4 #240 outpad +out:ppeaki_11_11_ 9 0 0 1 #241 outpad +out:ppeaki_12_12_ 7 0 0 5 #242 outpad +out:ppeaki_13_13_ 8 0 0 2 #243 outpad +out:ppeaki_14_14_ 8 0 0 3 #244 outpad +out:ppeaki_15_15_ 8 0 0 4 #245 outpad +out:ppeaki_1_1_ 7 0 0 6 #246 outpad +out:ppeaki_2_2_ 9 0 0 2 #247 outpad +out:ppeaki_3_3_ 9 0 0 3 #248 outpad +out:ppeaki_4_4_ 9 0 0 4 #249 outpad +out:ppeaki_5_5_ 9 0 0 5 #250 outpad +out:ppeaki_6_6_ 9 0 0 6 #251 outpad +out:ppeaki_7_7_ 9 0 0 7 #252 outpad +out:ppeaki_8_8_ 6 0 0 3 #253 outpad +out:ppeaki_9_9_ 8 0 0 5 #254 outpad +out:ppeakp_0_0_ 12 0 0 3 #255 outpad +out:ppeakp_10_10_ 7 0 0 7 #256 outpad +out:ppeakp_11_11_ 6 15 0 0 #257 outpad +out:ppeakp_12_12_ 6 15 0 1 #258 outpad +out:ppeakp_13_13_ 3 15 0 0 #259 outpad +out:ppeakp_14_14_ 7 15 0 0 #260 outpad +out:ppeakp_15_15_ 6 0 0 4 #261 outpad +out:ppeakp_1_1_ 15 9 0 0 #262 outpad +out:ppeakp_2_2_ 13 15 0 0 #263 outpad +out:ppeakp_3_3_ 12 0 0 4 #264 outpad +out:ppeakp_4_4_ 13 0 0 2 #265 outpad +out:ppeakp_5_5_ 10 0 0 5 #266 outpad +out:ppeakp_6_6_ 8 0 0 6 #267 outpad +out:ppeakp_7_7_ 5 15 0 5 #268 outpad +out:ppeakp_8_8_ 3 0 0 4 #269 outpad +out:ppeakp_9_9_ 4 0 0 6 #270 outpad +out:ppeaks_0_0_ 11 15 0 3 #271 outpad +out:ppeaks_10_10_ 0 9 0 0 #272 outpad +out:ppeaks_11_11_ 6 15 0 2 #273 outpad +out:ppeaks_12_12_ 5 15 0 6 #274 outpad +out:ppeaks_13_13_ 3 0 0 5 #275 outpad +out:ppeaks_14_14_ 10 0 0 6 #276 outpad +out:ppeaks_15_15_ 0 8 0 0 #277 outpad +out:ppeaks_1_1_ 9 15 0 1 #278 outpad +out:ppeaks_2_2_ 10 15 0 1 #279 outpad +out:ppeaks_3_3_ 11 0 0 6 #280 outpad +out:ppeaks_4_4_ 15 10 0 0 #281 outpad +out:ppeaks_5_5_ 12 15 0 1 #282 outpad +out:ppeaks_6_6_ 10 0 0 7 #283 outpad +out:ppeaks_7_7_ 10 15 0 2 #284 outpad +out:ppeaks_8_8_ 0 7 0 0 #285 outpad +out:ppeaks_9_9_ 2 0 0 2 #286 outpad +out:prd_0_0_ 8 15 0 2 #287 outpad +out:pwr_0_0_ 6 0 0 5 #288 outpad +pclk 1 0 0 2 #289 inpad +pirq_0_0_ 7 15 0 1 #290 inpad +preset 7 15 0 2 #291 inpad +preset_0_0_ 7 15 0 3 #292 inpad +tin_pdata_0_0_ 12 0 0 5 #293 inpad +tin_pdata_10_10_ 4 0 0 7 #294 inpad +tin_pdata_11_11_ 4 15 0 4 #295 inpad +tin_pdata_12_12_ 7 15 0 4 #296 inpad +tin_pdata_13_13_ 8 0 0 7 #297 inpad +tin_pdata_14_14_ 5 15 0 7 #298 inpad +tin_pdata_15_15_ 11 0 0 7 #299 inpad +tin_pdata_1_1_ 6 0 0 6 #300 inpad +tin_pdata_2_2_ 11 15 0 4 #301 inpad +tin_pdata_3_3_ 12 0 0 6 #302 inpad +tin_pdata_4_4_ 15 3 0 0 #303 inpad +tin_pdata_5_5_ 10 15 0 3 #304 inpad +tin_pdata_6_6_ 5 0 0 6 #305 inpad +tin_pdata_7_7_ 6 0 0 7 #306 inpad +tin_pdata_8_8_ 3 0 0 6 #307 inpad +tin_pdata_9_9_ 5 0 0 7 #308 inpad diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index f075c3f14a7..833846ae19e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -7,6 +7,7 @@ regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer +regression_tests/vtr_reg_strong/strong_ap/flatrecon_full_legalizer regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks