SystemCore Errant Voltage Testing

[jasondaming]

Is "tell me if I can wire 12V to any pin on the systemcore" the type of test you would want any of us to try? I do think it will happen in practice but I also don't want to break it if it would be expected that this would currently fail and we wouldn't learn anything from this. Maybe you have already tried it?

https://www.chiefdelphi.com/t/frc-1678-citrus-circuits-systemcore-alpha-testing-thread/506842/37

[Kevin-OConnor]

I don't think is a test Alpha teams need to run. As mentioned in #187 the Systemcore Smart IO circuit is being modified based on feedback regarding pull-up/pull-down. This makes testing of the protection of the current SmartIO pins likely to be invalidated.

As indicated in the spec PDF the following pins are 24 tolerant (i.e. they should not be damaged by connection to 24V):

• CAN
• Smart IO VOut
• Smart IO Signal
• I2C VOut
• I2C SCL/SDA

Ground pins on the Smart IO and I2C are protected by an internal fuse which would likely blow if an external power source (e.g. a +12V power wire) contacts these pins. To my understanding it is not intended to be user serviceable but is likely possible to replace for ambitious users (final details of RMA/repair options/etc. still being worked on). This is similar to the protection on roboRIO. Protecting the ground pins against the "dead short" case in a completely non-destructive way would have driven either or both of cost/complexity and performance (i.e. voltage drop) undesirably. Connecting any Systemcore sourced power direct to Ground should result in the overcurrent protection on that source tripping before the fuse blows.

Testing of this specification is part of Limelight's design validation testing.