Add pass to read/write files with memory initialization data #10
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Per the inquiry in issue #1 I put together a pass to extract memory initialization data into separate files:
I hooked it up as an option in
synth_quicklogic:Feel free to suggest better naming.
Some points to discuss:
The format of the data: Currently it's 36 bits of hex-encoded data per line.
Handling of undef bits: There's no handling of it as of now, so when the data is being written all x-bits are replaced with zero.
Retaining of the
RAM_INITparameter: The data in theRAM_INITparameter is kept on the cells even after being written down into the extra files. One thing to consider is resetting it so that it doesn't take up space in the output BLIF/EDIF/Verilog files. I don't know if resetting it to a fully-sized vector of undef bits will lead to a compressed representation in any of the output formats. Another option is to reset it to a zero-sized value.