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This PR extends the DPL TimerP API with new helper functions to simplify
and safely configure timer registers on AM62Ax/AM62Px devices.

1. Add TimerP helper for TIMER_TOWR

  • Introduces a new API to configure the TIMER_TOWR (Timer Overflow Wrapper Register).
  • TIMER_TOWR is a 16-bit register that defines how many overflow events are masked before an interrupt is generated.
  • Example: Writing 3 raises the overflow interrupt only on the third overflow occurrence.

2. Add TimerP_setCompare for TIMER_TMAR

  • Adds the TimerP_setCompare() function to configure TIMER_TMAR.
  • TIMER_TMAR stores the compare value: when the counter matches it, a compare event is triggered.
  • This allows applications to set the compare register through the DPL API without direct register writes.

3. Add TimerP_configPwm() helper

  • Introduces TimerP_configPwm() to configure a GP timer for PWM output.
  • Programs TLDR, TCRR, and TMAR based on frequency and duty cycle, using a nanosecond timebase and 32-bit counter range.
  • Provides a single, validated entry point for PWM configuration.

Introduce a new helper in TimerP to configure the TIMER_TOWR register.

- TIMER_TOWR (Timer Overflow Wrapper Register) is 16-bit wide and
  defines how many overflow events are masked before an interrupt is
  generated.
- For example, writing 3 causes the timer to raise the overflow
  interrupt only on the third overflow occurrence.
- This allows coarser interrupt pacing and can help reduce ISR load.

The new function  provides a simple and safe way
to program this register.

Signed-off-by: Rafael V. Volkmer <[email protected]>
The TIMER_TMAR register stores the timer compare value. When the
counter matches this value, a compare event is triggered.

This commit adds the TimerP_setCompare() function to allow setting the
compare value through the DPL API, enabling users to configure the
timer compare register without direct register access.

Signed-off-by: Rafael V. Volkmer <[email protected]>
Introduce TimerP_configPwm() to configure the GP timer for PWM output.
The helper programs TLDR/TCRR/TMAR based on frequency and duty cycle,
using a nanosecond timebase and a 32-bit counter range.

This provides a safer, single entry point to set PWM frequency and duty
cycle while preserving the DPL timer semantics.

Signed-off-by: Rafael V. Volkmer <[email protected]>
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