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1. RTL-Digital-Designs RTL-Digital-Designs Public

   Verilog codes of Digital systems

   Verilog

2. Half_adder-sv-verification Half_adder-sv-verification Public

   This repository contains a SystemVerilog-based testbench developed for functional verification of digital designs. The testbench includes comprehensive simulation components such as: Generator, Dri…

   SystemVerilog

3. FSM-based-ATM-design FSM-based-ATM-design Public

   A Verilog-based FSM (Finite State Machine) design that simulates the core functionality of an ATM system, including PIN verification, transaction processing, and state transitions. Designed for sim…

   Verilog

4. Shift_and_add_Multiplier Shift_and_add_Multiplier Public

   This project implements a Shift and Add Multiplier, a classic sequential multiplication algorithm used in digital systems. It multiplies two binary numbers by performing a series of shifts and addi…

   Verilog

5. Asynchronous_FIFO Asynchronous_FIFO Public

   Verilog based Asynchronous FIFO Design for safe data transfer between two clock domains. Includes full/empty logic, CDC Techniques, testbench, and simulation support

   Verilog

6. Single_Port_RAM_memory Single_Port_RAM_memory Public

   This repository contains a SystemVerilog-based testbench developed for functional verification of digital designs. The testbench includes comprehensive simulation components such as: Generator, Dri…

   SystemVerilog