Adding CLIC (Core-Local Interrupt Controller) support to VexRiscv SMP CPU for LiteX SoC #10
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This PR is implementation of CLIC support for the VexRiscv SMP CPU core in the LiteX framework. CLIC provides advanced interrupt handling capabilities with up to 4096 interrupts and 8-bit priority levels.
It could be tested with:
cd pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/ext/VexRiscvsbt "runMain vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen --with-clic true --cpu-count 1"VexRiscv changes can be found in VexRiscv branch.