[hw/prim] Adapted primitives to no longer require primgen.py

hw/ip/prim/README.md

@@ -116,24 +116,6 @@ implemented by as many other libraries as needed.
 
 Technology libraries are referenced by their name.
 
-### Technology library discovery
-
-In many cases, technology libraries contain vendor-specific code which cannot be
-shared widely or openly. Therefore, a FuseSoC looks for available technology
-libraries at build time, and makes all libraries it finds available.
-
-The discovery is performed based on the agreed-on naming scheme for primitives.
-
-- FuseSoC scans all libraries (e.g. as specified by its `--cores-root` command
-  line argument) for cores.
-- All cores with a name matching `lowrisc:prim_TECHLIBNAME:PRIMNAME`
-  are considered. `TECHLIBNAME` is then added to the list of technology
-  libraries.
-
-After the discovery process has completed, a script (`primgen`) creates
-- an abstract primitive (see above), and
-- an entry in the `prim_pkg` package in the form of `prim_pkg::ImplTechlibname`
-  to identify the technology library by its name.
 
 ## User Guide
 
@@ -201,29 +183,15 @@ targets:
 
 To create a technology library follow these steps:
 
-- Choose a name for the new technology library. Names are all lower-case.
-  To ease sharing of technology libraries it is encouraged to pick a very
-  specific name, e.g. `tsmc40lp`, and not `asic`.
-- Copy the `prim_generic` folder into an arbitrary location (can be outside
-  of this repository). Name the folder `prim_YOURLIBRARYNAME`.
-- Replace the word `generic` everywhere with the name of your technology
-  library. This includes
-  - file and directory names (e.g. `prim_generic_ram1p.sv` becomes
-    `prim_tsmc40lp_ram1p.sv`),
-  - module names (e.g. `prim_generic_ram1p` becomes `prim_tsmc40lp_ram1p`), and
-  - all other references (grep for it!).
-- Implement all primitives. Replace the module body of the generic
-  implementation with a technology-specific implementation as needed. Do *not*
-  modify the list of ports or parameters in any way!
-
-## Implementation details
-
-Technology-dependent primitives are implemented as a FuseSoC generator. The
-core of the primitive (e.g. `lowrisc:prim:rom` in `prim/prim_rom.core`) calls
-a FuseSoC generator. This generator is the script `util/primgen.py`. As input,
-the script receives a list of all cores found by FuseSoC anywhere in its search
-path. The script then looks through the cores FuseSoC discovered and extracts
-a list of technology libraries out of it. It then goes on to create the
-abstract primitive (copying over the list of parameters and ports from the
-generic implementation), and an associated core file, which depends on all
-technology-dependent libraries that were found.
+1. Choose a name for the new technology library. Names are all lower-case.
+   To ease sharing of technology libraries it is encouraged to pick a very specific name, e.g. `tsmc40lp`, and not `asic`.
+2. Copy the `prim_generic` folder into an arbitrary location (can be outside of this repository). Name the folder `prim_YOURLIBRARYNAME`.
+3. Replace the word `generic` everywhere with the name of your technology library. This includes
+    - file and directory names (e.g. `prim_generic_ram1p.sv` becomes
+      `prim_tsmc40lp_ram1p.sv`),
+    - module names (e.g. `prim_generic_ram1p` becomes `prim_tsmc40lp_ram1p`), and
+    - all other references (grep for it!).
+4. Implement all primitives. Replace the module body of the generic implementation with a technology-specific implementation as needed.
+   Do *not* modify the list of ports or parameters in any way!
+5. Add the new technology library to the enum in `prim_pkg.sv` with a value in the form `prim_pkg::ImplTechlibname`.
+6. For each of the technology library's primitives add an instantiation to the associated wrapper module in `rtl/`.

hw/ip/prim/prim_and2.core

@@ -6,11 +6,16 @@ CAPI=2:
 name: "lowrisc:prim:and2"
 description: "Generic 2-input and"
 filesets:
-  primgen_dep:
+  files_rtl:
     depend:
       - lowrisc:prim:prim_pkg
-      - lowrisc:prim:primgen
       - lowrisc:prim:assert
+      - lowrisc:prim_xilinx:and2:0
+      - lowrisc:prim_generic:and2:0
+      - lowrisc:prim_xilinx_ultrascale:and2:0
+    files:
+      - rtl/prim_and2.sv
+    file_type: systemVerilogSource
 
   files_verilator_waiver:
     depend:
@@ -31,18 +36,10 @@ filesets:
       # common waivers
       - lowrisc:lint:common
 
-generate:
-  impl:
-    generator: primgen
-    parameters:
-      prim_name: and2
-
 targets:
   default:
     filesets:
       - tool_verilator   ? (files_verilator_waiver)
       - tool_ascentlint  ? (files_ascentlint_waiver)
       - tool_veriblelint ? (files_veriblelint_waiver)
-      - primgen_dep
-    generate:
-      - impl
+      - files_rtl

hw/ip/prim/prim_buf.core

@@ -6,11 +6,16 @@ CAPI=2:
 name: "lowrisc:prim:buf"
 description: "Generic buffer"
 filesets:
-  primgen_dep:
+  files_rtl:
     depend:
       - lowrisc:prim:prim_pkg
-      - lowrisc:prim:primgen
       - lowrisc:prim:assert
+      - lowrisc:prim_xilinx:buf:0
+      - lowrisc:prim_xilinx_ultrascale:buf:0
+      - lowrisc:prim_generic:buf:0
+    files:
+      - rtl/prim_buf.sv
+    file_type: systemVerilogSource
 
   files_verilator_waiver:
     depend:
@@ -31,18 +36,10 @@ filesets:
       # common waivers
       - lowrisc:lint:common
 
-generate:
-  impl:
-    generator: primgen
-    parameters:
-      prim_name: buf
-
 targets:
   default:
     filesets:
       - tool_verilator   ? (files_verilator_waiver)
       - tool_ascentlint  ? (files_ascentlint_waiver)
       - tool_veriblelint ? (files_veriblelint_waiver)
-      - primgen_dep
-    generate:
-      - impl
+      - files_rtl

hw/ip/prim/prim_clock_buf.core

@@ -6,11 +6,16 @@ CAPI=2:
 name: "lowrisc:prim:clock_buf"
 description: "Generic clock buffer"
 filesets:
-  primgen_dep:
+  files_rtl:
     depend:
       - lowrisc:prim:prim_pkg
-      - lowrisc:prim:primgen
       - lowrisc:prim:assert
+      - lowrisc:prim_xilinx:clock_buf:0
+      - lowrisc:prim_xilinx_ultrascale:clock_buf:0
+      - lowrisc:prim_generic:clock_buf:0
+    files:
+      - rtl/prim_clock_buf.sv
+    file_type: systemVerilogSource
 
   files_verilator_waiver:
     depend:
@@ -30,18 +35,10 @@ filesets:
       # common waivers
       - lowrisc:lint:common
 
-generate:
-  impl:
-    generator: primgen
-    parameters:
-      prim_name: clock_buf
-
 targets:
   default:
     filesets:
       - tool_verilator   ? (files_verilator_waiver)
       - tool_ascentlint  ? (files_ascentlint_waiver)
       - tool_veriblelint ? (files_veriblelint_waiver)
-      - primgen_dep
-    generate:
-      - impl
+      - files_rtl

hw/ip/prim/prim_clock_div.core

@@ -6,10 +6,14 @@ CAPI=2:
 name: "lowrisc:prim:clock_div"
 description: "Generic clock divide"
 filesets:
-  primgen_dep:
+  files_rtl:
     depend:
       - lowrisc:prim:prim_pkg
-      - lowrisc:prim:primgen
+      - lowrisc:prim_generic:clock_div:0
+      - lowrisc:prim_xilinx_ultrascale:clock_div:0
+    files:
+      - rtl/prim_clock_div.sv
+    file_type: systemVerilogSource
 
   files_verilator_waiver:
     depend:
@@ -29,18 +33,10 @@ filesets:
       # common waivers
       - lowrisc:lint:common
 
-generate:
-  impl:
-    generator: primgen
-    parameters:
-      prim_name: clock_div
-
 targets:
   default:
     filesets:
       - tool_verilator   ? (files_verilator_waiver)
       - tool_ascentlint  ? (files_ascentlint_waiver)
       - tool_veriblelint ? (files_veriblelint_waiver)
-      - primgen_dep
-    generate:
-      - impl
+      - files_rtl

hw/ip/prim/prim_clock_gating.core

@@ -6,11 +6,15 @@ CAPI=2:
 name: "lowrisc:prim:clock_gating"
 description: "Clock gating primitives"
 filesets:
-  primgen_dep:
+  files_rtl:
     depend:
       - lowrisc:prim:prim_pkg
-      - lowrisc:prim:primgen
-
+      - lowrisc:prim_generic:clock_gating:0
+      - lowrisc:prim_xilinx:clock_gating:0
+      - lowrisc:prim_xilinx_ultrascale:clock_gating:0
+    files:
+      - rtl/prim_clock_gating.sv
+    file_type: systemVerilogSource
 
   files_verilator_waiver:
     depend:
@@ -30,18 +34,10 @@ filesets:
       # common waivers
       - lowrisc:lint:common
 
-generate:
-  impl:
-    generator: primgen
-    parameters:
-      prim_name: clock_gating
-
 targets:
   default:
     filesets:
       - tool_verilator   ? (files_verilator_waiver)
       - tool_ascentlint  ? (files_ascentlint_waiver)
       - tool_veriblelint ? (files_veriblelint_waiver)
-      - primgen_dep
-    generate:
-      - impl
+      - files_rtl

hw/ip/prim/prim_clock_inv.core

@@ -6,11 +6,14 @@ CAPI=2:
 name: "lowrisc:prim:clock_inv"
 description: "Clock inverter with scanmode bypass mux"
 filesets:
-  primgen_dep:
+  files_rtl:
     depend:
       - lowrisc:prim:prim_pkg
-      - lowrisc:prim:primgen
-
+      - lowrisc:prim_generic:clock_inv:0
+      - lowrisc:prim_xilinx_ultrascale:clock_inv:0
+    files:
+      - rtl/prim_clock_inv.sv
+    file_type: systemVerilogSource
 
   files_verilator_waiver:
     depend:
@@ -30,18 +33,10 @@ filesets:
       # common waivers
       - lowrisc:lint:common
 
-generate:
-  impl:
-    generator: primgen
-    parameters:
-      prim_name: clock_inv
-
 targets:
   default:
     filesets:
       - tool_verilator   ? (files_verilator_waiver)
       - tool_ascentlint  ? (files_ascentlint_waiver)
       - tool_veriblelint ? (files_veriblelint_waiver)
-      - primgen_dep
-    generate:
-      - impl
+      - files_rtl

hw/ip/prim/prim_clock_mux2.core

@@ -6,11 +6,15 @@ CAPI=2:
 name: "lowrisc:prim:clock_mux2"
 description: "2-input clock multiplexer"
 filesets:
-  primgen_dep:
+  files_rtl:
     depend:
       - lowrisc:prim:prim_pkg
-      - lowrisc:prim:primgen
-
+      - lowrisc:prim_generic:clock_mux2:0
+      - lowrisc:prim_xilinx_ultrascale:clock_mux2:0
+      - lowrisc:prim_xilinx:clock_mux2:0
+    files:
+      - rtl/prim_clock_mux2.sv
+    file_type: systemVerilogSource
 
   files_verilator_waiver:
     depend:
@@ -30,18 +34,10 @@ filesets:
       # common waivers
       - lowrisc:lint:common
 
-generate:
-  impl:
-    generator: primgen
-    parameters:
-      prim_name: clock_mux2
-
 targets:
   default:
     filesets:
       - tool_verilator   ? (files_verilator_waiver)
       - tool_ascentlint  ? (files_ascentlint_waiver)
       - tool_veriblelint ? (files_veriblelint_waiver)
-      - primgen_dep
-    generate:
-      - impl
+      - files_rtl

hw/ip/prim/prim_flash.core

@@ -6,16 +6,13 @@ CAPI=2:
 name: "lowrisc:prim:flash"
 description: "Flash memory"
 filesets:
-  primgen_dep:
+  files_rtl:
     depend:
       - lowrisc:prim:prim_pkg
-      - lowrisc:prim:primgen
-      # TODO olofk/fusesoc#404: The below dependency is already added to prim_generic_flash.core.
-      # However, the generator for the prim:ram1p does not kick in, causing compile errors.
-      - lowrisc:prim:ram_1p
-      - lowrisc:prim:clock_inv
-      - lowrisc:prim:clock_gating
-
+      - lowrisc:prim_generic:flash:0
+    files:
+      - rtl/prim_flash.sv
+    file_type: systemVerilogSource
 
   files_verilator_waiver:
     depend:
@@ -35,18 +32,10 @@ filesets:
       # common waivers
       - lowrisc:lint:common
 
-generate:
-  impl:
-    generator: primgen
-    parameters:
-      prim_name: flash
-
 targets:
   default:
     filesets:
       - tool_verilator   ? (files_verilator_waiver)
       - tool_ascentlint  ? (files_ascentlint_waiver)
       - tool_veriblelint ? (files_veriblelint_waiver)
-      - primgen_dep
-    generate:
-      - impl
+      - files_rtl