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Aaron-HartwigAaron-Hartwig
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gimlet-seq-server: use generated state machine status types in ringbuf (#2104)
This PR makes use of the generated state machine status types we get from the FPGA register map in the ringbuf, making it a bit more human-friendly to tell what is going on, particularly where we got stuck when failing to sequence. Further enhancements could be made if we implemented something like #2103 to easily give detailed information about the status of readbacks (power goods, etc). This pulls in some updated register map descriptions for pieces related to sequencing (see oxidecomputer/quartz@f9b6e3e). All of this is quality-of-life improvements for triaging Gimlet sequencing problems.
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7 files changed

+87
-88
lines changed

7 files changed

+87
-88
lines changed

‎app/gimlet/base.toml‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -170,8 +170,8 @@ notifications = ["timer", "vcore"]
170170
copy-to-archive = ["register_defs"]
171171

172172
[tasks.gimlet_seq.config]
173-
fpga_image = "fpga-b.bin"
174-
register_defs = "gimlet-regs-b.json"
173+
fpga_image = "fpga.bin"
174+
register_defs = "gimlet-regs.json"
175175

176176
[tasks.gimlet_inspector]
177177
name = "task-gimlet-inspector"

‎build/fpga-regmap/src/lib.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -230,7 +230,7 @@ fn write_reg_fields(
230230
output,
231231
"
232232
{prefix} impl TryFrom<u8> for {encode_name} {{
233-
{prefix} type Error = ();
233+
{prefix} type Error = u8;
234234
{prefix} fn try_from(x: u8) -> Result<Self, Self::Error> {{
235235
{prefix} use crate::{parent_chain}::{encode_name}::*;
236236
{prefix} let x_masked = x & {inst_name};
@@ -248,7 +248,7 @@ fn write_reg_fields(
248248
}
249249
writeln!(
250250
output,
251-
"{prefix} _ => Err(()),
251+
"{prefix} _ => Err(x),
252252
{prefix} }}
253253
{prefix} }}
254254
{prefix} }}\n"

‎drv/gimlet-seq-server/README.md‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,2 @@
11
FPGA images and collateral (bin, json, html) are generated by
2-
[this build](https://github.com/oxidecomputer/quartz/actions/runs/14455499093/job/40537695566).
2+
[this build](https://github.com/oxidecomputer/quartz/actions/runs/15784794718/job/44498722562).

‎drv/gimlet-seq-server/fpga-b.bin‎ renamed to ‎drv/gimlet-seq-server/fpga.bin‎

132 KB
Binary file not shown.

‎drv/gimlet-seq-server/gimlet-regs-b.html‎ renamed to ‎drv/gimlet-seq-server/gimlet-regs.html‎

Lines changed: 31 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -1430,8 +1430,7 @@ <h1>gimlet_seq_fpga</h1>
14301430
<td class="FieldDesc" colspan="1*">3</td>
14311431
<td class="FieldDesc" colspan="2*">r</td>
14321432
<td class="FieldDesc" colspan="2*">0x0</td>
1433-
<td class="FieldDesc" colspan="14">Readback for V0P9_SP3_VDD_SOC_S5_A1 rail
1434-
(SP3_TO_SEQ_V0P9_VDD_SOC_S5_PG)
1433+
<td class="FieldDesc" colspan="14">Readback for V0P9_SP3_VDD_SOC_S5_A1 rail from U490 (SP3_TO_SEQ_V0P9_VDD_SOC_S5_PG net)
14351434
</td>
14361435
</tr>
14371436
<tr class="cat26" style="display: none">
@@ -1440,8 +1439,7 @@ <h1>gimlet_seq_fpga</h1>
14401439
<td class="FieldDesc" colspan="1*">2</td>
14411440
<td class="FieldDesc" colspan="2*">r</td>
14421441
<td class="FieldDesc" colspan="2*">0x0</td>
1443-
<td class="FieldDesc" colspan="14">Readback for V1P8_SP3_VDD_18_S5_A rail
1444-
(SP3_TO_SEQ_V1P8_S5_PG)
1442+
<td class="FieldDesc" colspan="14">Readback for V1P8_SP3_VDD_18_S5_A rail from U486 (SP3_TO_SEQ_V1P8_S5_PG net)
14451443
</td>
14461444
</tr>
14471445
<tr class="cat26" style="display: none">
@@ -1450,8 +1448,7 @@ <h1>gimlet_seq_fpga</h1>
14501448
<td class="FieldDesc" colspan="1*">1</td>
14511449
<td class="FieldDesc" colspan="2*">r</td>
14521450
<td class="FieldDesc" colspan="2*">0x0</td>
1453-
<td class="FieldDesc" colspan="14">Readback for V3P3_SP3_VDD_33_S5_A1 rail
1454-
(SP3_TO_SEQ_V3P3_S5_PG)
1451+
<td class="FieldDesc" colspan="14">Readback for V3P3_SP3_VDD_33_S5_A1 rail from U483 (SP3_TO_SEQ_V3P3_S5_PG net)
14551452
</td>
14561453
</tr>
14571454
<tr class="cat26" style="display: none">
@@ -1460,8 +1457,7 @@ <h1>gimlet_seq_fpga</h1>
14601457
<td class="FieldDesc" colspan="1*">0</td>
14611458
<td class="FieldDesc" colspan="2*">r</td>
14621459
<td class="FieldDesc" colspan="2*">0x0</td>
1463-
<td class="FieldDesc" colspan="14">Readback for V1P5_SP_VDD_RTC_A1 rail.
1464-
(SP3_TO_SEQ_RTC_V1P5_EN - a poor net name)
1460+
<td class="FieldDesc" colspan="14">Readback for V1P5_SP_VDD_RTC_A1 rail from U494 (SP3_TO_SEQ_RTC_V1P5_PG net)
14651461
</td>
14661462
</tr>
14671463
<tr class="Register">
@@ -1510,7 +1506,7 @@ <h1>gimlet_seq_fpga</h1>
15101506
<td class="FieldDesc" colspan="2*">r</td>
15111507
<td class="FieldDesc" colspan="2*">0x0</td>
15121508
<td class="FieldDesc" colspan="14">Asserted by AMD after PWR_GOOD is asserted by sequencer
1513-
should be here in: min 15ms, max of 20.4ms(SP3_TO_SEQ_PWROK_V3P3 net)
1509+
should be here in: min 15ms, max of 20.4ms (SP3_TO_SEQ_PWROK_V3P3 net)
15141510
</td>
15151511
</tr>
15161512
<tr class="cat27" style="display: none">
@@ -1519,7 +1515,7 @@ <h1>gimlet_seq_fpga</h1>
15191515
<td class="FieldDesc" colspan="1*">1</td>
15201516
<td class="FieldDesc" colspan="2*">r</td>
15211517
<td class="FieldDesc" colspan="2*">0x0</td>
1522-
<td class="FieldDesc" colspan="14">SP3_TO_SP_SLP_S5 inversion of signal from AMD CPU, Used
1518+
<td class="FieldDesc" colspan="14">SP3_TO_SEQ_SLP_S5_L inversion of signal from AMD CPU, Used
15231519
at beginning of GroupB state machine
15241520
</td>
15251521
</tr>
@@ -1529,7 +1525,7 @@ <h1>gimlet_seq_fpga</h1>
15291525
<td class="FieldDesc" colspan="1*">0</td>
15301526
<td class="FieldDesc" colspan="2*">r</td>
15311527
<td class="FieldDesc" colspan="2*">0x0</td>
1532-
<td class="FieldDesc" colspan="14">SP3_TO_SP_SLP_S3 inversion of signal from AMD CPU, Used
1528+
<td class="FieldDesc" colspan="14">SP3_TO_SEQ_SLP_S3_L inversion of signal from AMD CPU, Used
15331529
at beginning of GroupB state machine
15341530
</td>
15351531
</tr>
@@ -1570,9 +1566,7 @@ <h1>gimlet_seq_fpga</h1>
15701566
<td class="FieldDesc" colspan="1*">7</td>
15711567
<td class="FieldDesc" colspan="2*">r</td>
15721568
<td class="FieldDesc" colspan="2*">0x0</td>
1573-
<td class="FieldDesc" colspan="14">Readback from V3P3_SYS_A0 rail (PWR_CONT_DIMM_ABCD_PG1)
1574-
PG1 from ISL68224 U352, should be configured to represent
1575-
V3P3_SYS_A0 rail status
1569+
<td class="FieldDesc" colspan="14">Readback from V3P3_SYS_A0 rail from U360 (V3P3_SYS_TO_SEQ_PG net)
15761570
</td>
15771571
</tr>
15781572
<tr class="cat28" style="display: none">
@@ -1581,7 +1575,7 @@ <h1>gimlet_seq_fpga</h1>
15811575
<td class="FieldDesc" colspan="1*">6</td>
15821576
<td class="FieldDesc" colspan="2*">r</td>
15831577
<td class="FieldDesc" colspan="2*">None</td>
1584-
<td class="FieldDesc" colspan="14">Readback for V1P8_SP3_VDD_18_A0 rail (SEQ_V1P8_SP3_VDD_PG_L) inverted
1578+
<td class="FieldDesc" colspan="14">Readback for V1P8_SP3_VDD_18_A0 rail from UP38. As indicated by SEQ_V1P8_SP3_VDD_PG from U352.
15851579
</td>
15861580
</tr>
15871581
<tr class="cat28" style="display: none">
@@ -1590,7 +1584,7 @@ <h1>gimlet_seq_fpga</h1>
15901584
<td class="FieldDesc" colspan="1*">5</td>
15911585
<td class="FieldDesc" colspan="2*">r</td>
15921586
<td class="FieldDesc" colspan="2*">None</td>
1593-
<td class="FieldDesc" colspan="14">Readback for VTT_EFGH_A0 rail (VTT_EFGH_A0_TO_SEQ_PG_L) inverted
1587+
<td class="FieldDesc" colspan="14">Readback for VTT_EF_A0 and VTT_GH_A0 rails. This is a logical AND of VTT_EF_A0_TO_SEQ_PG (U445) and VTT_GH_A0_TO_SEQ_PG (U564)
15941588
</td>
15951589
</tr>
15961590
<tr class="cat28" style="display: none">
@@ -1599,7 +1593,7 @@ <h1>gimlet_seq_fpga</h1>
15991593
<td class="FieldDesc" colspan="1*">4</td>
16001594
<td class="FieldDesc" colspan="2*">r</td>
16011595
<td class="FieldDesc" colspan="2*">None</td>
1602-
<td class="FieldDesc" colspan="14">Readback for VTT_ABCD_A0 rail (VTT_ABCD_A0_TO_SEQ_PG_L) inverted
1596+
<td class="FieldDesc" colspan="14">Readback for VTT_AB_A0 and VTT_CD_A0 rails. This is a logical AND of VTT_AB_A0_TO_SEQ_PG (U432) and VTT_CD_A0_TO_SEQ_PG (U563)
16031597
</td>
16041598
</tr>
16051599
<tr class="cat28" style="display: none">
@@ -1630,7 +1624,7 @@ <h1>gimlet_seq_fpga</h1>
16301624
<td class="FieldDesc" colspan="1*">1</td>
16311625
<td class="FieldDesc" colspan="2*">r</td>
16321626
<td class="FieldDesc" colspan="2*">0x0</td>
1633-
<td class="FieldDesc" colspan="14">Readback from VPP_EFGH_A0 rail (PWR_CONT_DIMM_EFGH_PG0 net)
1627+
<td class="FieldDesc" colspan="14">Readback from VPP_EFGH_A0 rail from UP37. As indicated by PWR_CONT_DIMM_PG1 from U352.
16341628
</td>
16351629
</tr>
16361630
<tr class="cat28" style="display: none">
@@ -1639,7 +1633,7 @@ <h1>gimlet_seq_fpga</h1>
16391633
<td class="FieldDesc" colspan="1*">0</td>
16401634
<td class="FieldDesc" colspan="2*">r</td>
16411635
<td class="FieldDesc" colspan="2*">0x0</td>
1642-
<td class="FieldDesc" colspan="14">Readback from VPP_ABCD_A0 rail (PWR_CONT_DIMM_ABCD_PG0 net)
1636+
<td class="FieldDesc" colspan="14">Readback from VPP_ABCD_A0 rail from UP36. As indicated by PWR_CONT_DIMM_PG0 from U352.
16431637
</td>
16441638
</tr>
16451639
<tr class="Register">
@@ -1858,7 +1852,7 @@ <h1>gimlet_seq_fpga</h1>
18581852
<td class="FieldDesc" colspan="1*">5</td>
18591853
<td class="FieldDesc" colspan="2*">r</td>
18601854
<td class="FieldDesc" colspan="2*">0x0</td>
1861-
<td class="FieldDesc" colspan="14">Power good for V1P5_NIC_PCIE_MEM_A0HP (inverted NIC_TO_SEQ_V1P5D_PG_L net)
1855+
<td class="FieldDesc" colspan="14">Power good for V1P5_NIC_PCIE_MEM_A0HP from U360 (NIC_TO_SEQ_V1P5D_PG net)
18621856
</td>
18631857
</tr>
18641858
<tr class="cat32" style="display: none">
@@ -1867,7 +1861,7 @@ <h1>gimlet_seq_fpga</h1>
18671861
<td class="FieldDesc" colspan="1*">4</td>
18681862
<td class="FieldDesc" colspan="2*">r</td>
18691863
<td class="FieldDesc" colspan="2*">0x0</td>
1870-
<td class="FieldDesc" colspan="14">Power good for V1P5_NIC_AVDD_A0HP (inverted NIC_TO_SEQ_V1P5A_PG_L net)
1864+
<td class="FieldDesc" colspan="14">Power good for V1P5_NIC_AVDD_A0HP from U360 (NIC_TO_SEQ_V1P5A_PG net)
18711865
</td>
18721866
</tr>
18731867
<tr class="cat32" style="display: none">
@@ -1876,7 +1870,7 @@ <h1>gimlet_seq_fpga</h1>
18761870
<td class="FieldDesc" colspan="1*">3</td>
18771871
<td class="FieldDesc" colspan="2*">r</td>
18781872
<td class="FieldDesc" colspan="2*">0x0</td>
1879-
<td class="FieldDesc" colspan="14">Power good for V1P2_NIC_ETH (inverted NIC_TO_SEQ_V1P2_PG_L net)
1873+
<td class="FieldDesc" colspan="14">Power good for V1P2_NIC_ENET_A0HP from U424 (NIC_TO_SEQ_V1P2_ENET_PG net)
18801874
</td>
18811875
</tr>
18821876
<tr class="cat32" style="display: none">
@@ -1885,7 +1879,7 @@ <h1>gimlet_seq_fpga</h1>
18851879
<td class="FieldDesc" colspan="1*">2</td>
18861880
<td class="FieldDesc" colspan="2*">r</td>
18871881
<td class="FieldDesc" colspan="2*">0x0</td>
1888-
<td class="FieldDesc" colspan="14">Power good for V1P2_NIC_MDIO_A0HP (inverted NIC_TO_SEQ_V1P2_PG_L net)
1882+
<td class="FieldDesc" colspan="14">Power good for V1P2_NIC_MDIO_A0HP from U424 (inverted NIC_TO_SEQ_V1P2_PG_L net)
18891883
</td>
18901884
</tr>
18911885
<tr class="cat32" style="display: none">
@@ -1894,7 +1888,7 @@ <h1>gimlet_seq_fpga</h1>
18941888
<td class="FieldDesc" colspan="1*">1</td>
18951889
<td class="FieldDesc" colspan="2*">r</td>
18961890
<td class="FieldDesc" colspan="2*">0x0</td>
1897-
<td class="FieldDesc" colspan="14">Power good for V1P1_NIC_ETH_IO_A0HP (inverted NIC_TO_SEQ_V1P1_PG_L net)
1891+
<td class="FieldDesc" colspan="14">Power good for V1P1_NIC_ETH_IO_A0HP from U630 (inverted NIC_TO_SEQ_V1P1_PG_L net)
18981892
</td>
18991893
</tr>
19001894
<tr class="cat32" style="display: none">
@@ -1903,7 +1897,7 @@ <h1>gimlet_seq_fpga</h1>
19031897
<td class="FieldDesc" colspan="1*">0</td>
19041898
<td class="FieldDesc" colspan="2*">r</td>
19051899
<td class="FieldDesc" colspan="2*">0x0</td>
1906-
<td class="FieldDesc" colspan="14">Power good for V0P96_NIC_VDD_A0HP (PWR_CONT_NIC_PG0 net)
1900+
<td class="FieldDesc" colspan="14">Power good for V0P96_NIC_VDD_A0HP from U565 (PWR_CONT_NIC_PG0 net)
19071901
</td>
19081902
</tr>
19091903
<tr class="Register">
@@ -2972,9 +2966,7 @@ <h1>gimlet_seq_fpga</h1>
29722966
<td class="FieldDesc" colspan="1*">7</td>
29732967
<td class="FieldDesc" colspan="2*">r</td>
29742968
<td class="FieldDesc" colspan="2*">0x0</td>
2975-
<td class="FieldDesc" colspan="14">Readback from V3P3_SYS_A0 rail (PWR_CONT_DIMM_ABCD_PG1)
2976-
PG1 from ISL68224 U352, should be configured to represent
2977-
V3P3_SYS_A0 rail status
2969+
<td class="FieldDesc" colspan="14">Readback from V3P3_SYS_A0 rail from U360 (V3P3_SYS_TO_SEQ_PG net)
29782970
</td>
29792971
</tr>
29802972
<tr class="cat49" style="display: none">
@@ -2983,7 +2975,7 @@ <h1>gimlet_seq_fpga</h1>
29832975
<td class="FieldDesc" colspan="1*">6</td>
29842976
<td class="FieldDesc" colspan="2*">r</td>
29852977
<td class="FieldDesc" colspan="2*">None</td>
2986-
<td class="FieldDesc" colspan="14">Readback for V1P8_SP3_VDD_18_A0 rail (SEQ_V1P8_SP3_VDD_PG_L) inverted
2978+
<td class="FieldDesc" colspan="14">Readback for V1P8_SP3_VDD_18_A0 rail from UP38. As indicated by SEQ_V1P8_SP3_VDD_PG from U352.
29872979
</td>
29882980
</tr>
29892981
<tr class="cat49" style="display: none">
@@ -2992,7 +2984,7 @@ <h1>gimlet_seq_fpga</h1>
29922984
<td class="FieldDesc" colspan="1*">5</td>
29932985
<td class="FieldDesc" colspan="2*">r</td>
29942986
<td class="FieldDesc" colspan="2*">None</td>
2995-
<td class="FieldDesc" colspan="14">Readback for VTT_EFGH_A0 rail (VTT_EFGH_A0_TO_SEQ_PG_L) inverted
2987+
<td class="FieldDesc" colspan="14">Readback for VTT_EF_A0 and VTT_GH_A0 rails. This is a logical AND of VTT_EF_A0_TO_SEQ_PG (U445) and VTT_GH_A0_TO_SEQ_PG (U564)
29962988
</td>
29972989
</tr>
29982990
<tr class="cat49" style="display: none">
@@ -3001,7 +2993,7 @@ <h1>gimlet_seq_fpga</h1>
30012993
<td class="FieldDesc" colspan="1*">4</td>
30022994
<td class="FieldDesc" colspan="2*">r</td>
30032995
<td class="FieldDesc" colspan="2*">None</td>
3004-
<td class="FieldDesc" colspan="14">Readback for VTT_ABCD_A0 rail (VTT_ABCD_A0_TO_SEQ_PG_L) inverted
2996+
<td class="FieldDesc" colspan="14">Readback for VTT_AB_A0 and VTT_CD_A0 rails. This is a logical AND of VTT_AB_A0_TO_SEQ_PG (U432) and VTT_CD_A0_TO_SEQ_PG (U563)
30052997
</td>
30062998
</tr>
30072999
<tr class="cat49" style="display: none">
@@ -3032,7 +3024,7 @@ <h1>gimlet_seq_fpga</h1>
30323024
<td class="FieldDesc" colspan="1*">1</td>
30333025
<td class="FieldDesc" colspan="2*">r</td>
30343026
<td class="FieldDesc" colspan="2*">0x0</td>
3035-
<td class="FieldDesc" colspan="14">Readback from VPP_EFGH_A0 rail (PWR_CONT_DIMM_EFGH_PG0 net)
3027+
<td class="FieldDesc" colspan="14">Readback from VPP_EFGH_A0 rail from UP37. As indicated by PWR_CONT_DIMM_PG1 from U352.
30363028
</td>
30373029
</tr>
30383030
<tr class="cat49" style="display: none">
@@ -3041,7 +3033,7 @@ <h1>gimlet_seq_fpga</h1>
30413033
<td class="FieldDesc" colspan="1*">0</td>
30423034
<td class="FieldDesc" colspan="2*">r</td>
30433035
<td class="FieldDesc" colspan="2*">0x0</td>
3044-
<td class="FieldDesc" colspan="14">Readback from VPP_ABCD_A0 rail (PWR_CONT_DIMM_ABCD_PG0 net)
3036+
<td class="FieldDesc" colspan="14">Readback from VPP_ABCD_A0 rail from UP36. As indicated by PWR_CONT_DIMM_PG0 from U352.
30453037
</td>
30463038
</tr>
30473039
<tr class="Register">
@@ -3176,9 +3168,7 @@ <h1>gimlet_seq_fpga</h1>
31763168
<td class="FieldDesc" colspan="1*">7</td>
31773169
<td class="FieldDesc" colspan="2*">r</td>
31783170
<td class="FieldDesc" colspan="2*">0x0</td>
3179-
<td class="FieldDesc" colspan="14">Readback from V3P3_SYS_A0 rail (PWR_CONT_DIMM_ABCD_PG1)
3180-
PG1 from ISL68224 U352, should be configured to represent
3181-
V3P3_SYS_A0 rail status
3171+
<td class="FieldDesc" colspan="14">Readback from V3P3_SYS_A0 rail from U360 (V3P3_SYS_TO_SEQ_PG net)
31823172
</td>
31833173
</tr>
31843174
<tr class="cat52" style="display: none">
@@ -3187,7 +3177,7 @@ <h1>gimlet_seq_fpga</h1>
31873177
<td class="FieldDesc" colspan="1*">6</td>
31883178
<td class="FieldDesc" colspan="2*">r</td>
31893179
<td class="FieldDesc" colspan="2*">None</td>
3190-
<td class="FieldDesc" colspan="14">Readback for V1P8_SP3_VDD_18_A0 rail (SEQ_V1P8_SP3_VDD_PG_L) inverted
3180+
<td class="FieldDesc" colspan="14">Readback for V1P8_SP3_VDD_18_A0 rail from UP38. As indicated by SEQ_V1P8_SP3_VDD_PG from U352.
31913181
</td>
31923182
</tr>
31933183
<tr class="cat52" style="display: none">
@@ -3196,7 +3186,7 @@ <h1>gimlet_seq_fpga</h1>
31963186
<td class="FieldDesc" colspan="1*">5</td>
31973187
<td class="FieldDesc" colspan="2*">r</td>
31983188
<td class="FieldDesc" colspan="2*">None</td>
3199-
<td class="FieldDesc" colspan="14">Readback for VTT_EFGH_A0 rail (VTT_EFGH_A0_TO_SEQ_PG_L) inverted
3189+
<td class="FieldDesc" colspan="14">Readback for VTT_EF_A0 and VTT_GH_A0 rails. This is a logical AND of VTT_EF_A0_TO_SEQ_PG (U445) and VTT_GH_A0_TO_SEQ_PG (U564)
32003190
</td>
32013191
</tr>
32023192
<tr class="cat52" style="display: none">
@@ -3205,7 +3195,7 @@ <h1>gimlet_seq_fpga</h1>
32053195
<td class="FieldDesc" colspan="1*">4</td>
32063196
<td class="FieldDesc" colspan="2*">r</td>
32073197
<td class="FieldDesc" colspan="2*">None</td>
3208-
<td class="FieldDesc" colspan="14">Readback for VTT_ABCD_A0 rail (VTT_ABCD_A0_TO_SEQ_PG_L) inverted
3198+
<td class="FieldDesc" colspan="14">Readback for VTT_AB_A0 and VTT_CD_A0 rails. This is a logical AND of VTT_AB_A0_TO_SEQ_PG (U432) and VTT_CD_A0_TO_SEQ_PG (U563)
32093199
</td>
32103200
</tr>
32113201
<tr class="cat52" style="display: none">
@@ -3236,7 +3226,7 @@ <h1>gimlet_seq_fpga</h1>
32363226
<td class="FieldDesc" colspan="1*">1</td>
32373227
<td class="FieldDesc" colspan="2*">r</td>
32383228
<td class="FieldDesc" colspan="2*">0x0</td>
3239-
<td class="FieldDesc" colspan="14">Readback from VPP_EFGH_A0 rail (PWR_CONT_DIMM_EFGH_PG0 net)
3229+
<td class="FieldDesc" colspan="14">Readback from VPP_EFGH_A0 rail from UP37. As indicated by PWR_CONT_DIMM_PG1 from U352.
32403230
</td>
32413231
</tr>
32423232
<tr class="cat52" style="display: none">
@@ -3245,7 +3235,7 @@ <h1>gimlet_seq_fpga</h1>
32453235
<td class="FieldDesc" colspan="1*">0</td>
32463236
<td class="FieldDesc" colspan="2*">r</td>
32473237
<td class="FieldDesc" colspan="2*">0x0</td>
3248-
<td class="FieldDesc" colspan="14">Readback from VPP_ABCD_A0 rail (PWR_CONT_DIMM_ABCD_PG0 net)
3238+
<td class="FieldDesc" colspan="14">Readback from VPP_ABCD_A0 rail from UP36. As indicated by PWR_CONT_DIMM_PG0 from U352.
32493239
</td>
32503240
</tr>
32513241
<tr class="Register">

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