Support mixed size peripherals in support of espi post-code buffer #2278
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Initial implementation for larger espi peripheral with post-code buffer
mkeeter
approved these changes
Nov 5, 2025
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This PR adjusts the build system to support non-256byte sized peripherals and adds new FPGA functionality for keeping a per-boot espi post-code buffer which is reset by hardware on an A2 -> A0 transition. More software could be added to provide tooling to dump this out.
This also adjusts the memory map of the FPGA to align with the various MPU requirements which means that some addresses from shell history or human memory have moved, see the current FPGA map for more information.