Direct-Mapped-Cache-in-Verilog

This project implements the datapath of a direct mapped cache in Verilog as part of the undergraduate fourth year VLSI Design Lab project at BUET.

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
Images		Images
README.md		README.md
cache_controller.v		cache_controller.v
cache_mem.v		cache_mem.v
main.v		main.v
main_memory.v		main_memory.v
main_test.v		main_test.v
main_test2.v		main_test2.v
ram_data.txt		ram_data.txt
testbe.cr.mti		testbe.cr.mti
testbe.mpf		testbe.mpf
transcript		transcript
valid_init.txt		valid_init.txt
vsim.wlf		vsim.wlf
wave.do		wave.do
wb_test.v		wb_test.v

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