Facilitate RP2040 XIP-cache-as-RAM feature

src/cmake/rp2_common.cmake

@@ -3,9 +3,11 @@
 include(cmake/on_device.cmake)
 
 # PICO_CMAKE_CONFIG: PICO_NO_FLASH, Option to default all binaries to not use flash i.e. run from SRAM, type=bool, default=0, group=build, docref=cmake-binary-type-config
-option(PICO_NO_FLASH "Default binaries to not not use flash")
+option(PICO_NO_FLASH "Default binaries to not use flash")
 # PICO_CMAKE_CONFIG: PICO_COPY_TO_RAM, Option to default all binaries to copy code from flash to SRAM before running, type=bool, default=0, group=build, docref=cmake-binary-type-config
 option(PICO_COPY_TO_RAM "Default binaries to copy code to RAM when booting from flash")
+# PICO_CMAKE_CONFIG: PICO_USE_XIP_CACHE_AS_RAM, Option to use XIP cache as RAM storage for time critical functions, type=bool, default=0, group=build, docref=cmake-binary-type-config
+option(PICO_USE_XIP_CACHE_AS_RAM "Default binaries to run time critical code from XIP RAM")
 
 # COMMON
 pico_add_subdirectory(common/boot_picobin_headers)

src/rp2040/boot_stage2/BUILD.bazel

@@ -35,6 +35,7 @@ BOOT2_CHOICE_DEFINE_MAP["compile_time_choice"] = []
 cc_library(
     name = "config",
     hdrs = [
+        "asminclude/embedded_xip_cache_enable_block.inc.S",
         "asminclude/boot2_helpers/exit_from_boot2.S",
         "asminclude/boot2_helpers/read_flash_sreg.S",
         "asminclude/boot2_helpers/wait_ssi_ready.S",

src/rp2040/boot_stage2/CMakeLists.txt

@@ -31,6 +31,7 @@ pico_register_common_scope_var(PICO_DEFAULT_BOOT_STAGE2_FILE)
 set(PICO_BOOT_STAGE2_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "")
 
 pico_add_library(boot_stage2_headers)
+target_compile_definitions(boot_stage2_headers INTERFACE PICO_USE_XIP_CACHE_AS_RAM=$<IF:$<BOOL:${PICO_USE_XIP_CACHE_AS_RAM}>,1,0>)
 target_include_directories(boot_stage2_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
 
 # pico_define_boot_stage2(NAME SOURCES)

src/rp2040/boot_stage2/asminclude/embedded_xip_cache_enable_block.inc.S

@@ -0,0 +1,14 @@
+#include "hardware/regs/addressmap.h"
+#include "hardware/regs/xip.h"
+
+#if defined(PICO_USE_XIP_CACHE_AS_RAM) && PICO_USE_XIP_CACHE_AS_RAM
+    // Disable the XIP cache making its 16k of XIP RAM available for storage
+    ldr r0, =(REG_ALIAS_CLR_BITS + XIP_CTRL_BASE + XIP_CTRL_OFFSET)
+    movs r1, #XIP_CTRL_EN_BITS
+    str r1, [r0]
+#else
+    // Enable the XIP cache (hardware default)
+    ldr r0, =(REG_ALIAS_SET_BITS + XIP_CTRL_BASE + XIP_CTRL_OFFSET)
+    movs r1, #XIP_CTRL_EN_BITS
+    str r1, [r0]
+#endif

src/rp2040/boot_stage2/boot2_at25sf128a.S

@@ -266,6 +266,8 @@ configure_ssi:
 // Bus accesses to the XIP window will now be transparently serviced by the
 // external flash on cache miss. We are ready to run code from flash.
 
+#include "embedded_xip_cache_enable_block.inc.S"
+
 // Pull in standard exit routine
 #include "boot2_helpers/exit_from_boot2.S"
 

src/rp2040/boot_stage2/boot2_generic_03h.S

@@ -96,6 +96,8 @@ regular_func _stage2_boot
 // translated by the SSI into 03h read commands to the external flash (if cache is missed),
 // and the data will be returned to the bus.
 
+#include "embedded_xip_cache_enable_block.inc.S"
+
 // Pull in standard exit routine
 #include "boot2_helpers/exit_from_boot2.S"
 

src/rp2040/boot_stage2/boot2_is25lp080.S

@@ -248,6 +248,8 @@ configure_ssi:
 // We are now in XIP mode, with all transactions using Dual I/O and only
 // needing to send 24-bit addresses (plus mode bits) for each read transaction.
 
+#include "embedded_xip_cache_enable_block.inc.S"
+
 // Pull in standard exit routine
 #include "boot2_helpers/exit_from_boot2.S"
 

src/rp2040/boot_stage2/boot2_w25q080.S

@@ -268,6 +268,8 @@ configure_ssi:
 // Bus accesses to the XIP window will now be transparently serviced by the
 // external flash on cache miss. We are ready to run code from flash.
 
+#include "embedded_xip_cache_enable_block.inc.S"
+
 // Pull in standard exit routine
 #include "boot2_helpers/exit_from_boot2.S"
 

src/rp2040/boot_stage2/boot2_w25x10cl.S

@@ -187,6 +187,8 @@ regular_func _stage2_boot
 // We are now in XIP mode, with all transactions using Dual I/O and only
 // needing to send 24-bit addresses (plus mode bits) for each read transaction.
 
+#include "embedded_xip_cache_enable_block.inc.S"
+
 // Pull in standard exit routine
 #include "boot2_helpers/exit_from_boot2.S"
 

src/rp2_common/pico_crt0/BUILD.bazel

@@ -28,6 +28,14 @@ alias(
     }),
 )
 
+alias(
+    name = "copy_to_ram_using_xip_ram_linker_script",
+    actual = select({
+        "//bazel/constraint:rp2040": "//src/rp2_common/pico_crt0/rp2040:copy_to_ram_using_xip_ram_linker_script",
+        "//conditions:default": "//bazel:incompatible_cc_lib",
+    }),
+)
+
 alias(
     name = "no_flash_linker_script",
     actual = select({
@@ -37,6 +45,14 @@ alias(
     }),
 )
 
+alias(
+    name = "no_flash_using_xip_ram_linker_script",
+    actual = select({
+        "//bazel/constraint:rp2040": "//src/rp2_common/pico_crt0/rp2040:no_flash_using_xip_ram_linker_script",
+        "//conditions:default": "//bazel:incompatible_cc_lib",
+    }),
+)
+
 cc_library(
     name = "no_warn_rwx_flag",
     linkopts = select({

src/rp2_common/pico_crt0/CMakeLists.txt

@@ -7,6 +7,8 @@ if (NOT TARGET pico_crt0)
         target_sources(pico_crt0 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/crt0.S)
     endif()
 
+    target_compile_definitions(pico_crt0 INTERFACE PICO_USE_XIP_CACHE_AS_RAM=$<IF:$<BOOL:${PICO_USE_XIP_CACHE_AS_RAM}>,1,0>)
+
     pico_mirrored_target_link_libraries(pico_crt0 INTERFACE hardware_structs hardware_regs)
     target_link_libraries(pico_crt0 INTERFACE boot_picobin_headers pico_bootrom_headers)
 endif()

src/rp2_common/pico_crt0/crt0.S

@@ -11,6 +11,7 @@
 
 #include "hardware/regs/addressmap.h"
 #include "hardware/regs/sio.h"
+#include "hardware/regs/xip.h"
 #include "pico/binary_info/defs.h"
 #include "boot/picobin.h"
 #include "pico/bootrom.h"
@@ -457,6 +458,22 @@ hold_non_core0_in_bootrom:
     b _enter_vtable_in_r0
 1:
 
+#if PICO_RP2040 && PICO_NO_FLASH
+    #if PICO_USE_XIP_CACHE_AS_RAM
+        // Disable the XIP cache making its 16k of XIP RAM available for storage
+_disable_xip_cache:
+        ldr r0, =(REG_ALIAS_CLR_BITS + XIP_CTRL_BASE + XIP_CTRL_OFFSET)
+        movs r1, #XIP_CTRL_EN_BITS
+        str r1, [r0]
+    #else
+        // Enable the XIP cache (hardware default)
+_enable_xip_cache:
+        ldr r0, =(REG_ALIAS_SET_BITS + XIP_CTRL_BASE + XIP_CTRL_OFFSET)
+        movs r1, #XIP_CTRL_EN_BITS
+        str r1, [r0]
+    #endif
+#endif
+
 #if !PICO_RP2040 && PICO_EMBED_XIP_SETUP && !PICO_NO_FLASH
     // Execute boot2 on the core 0 stack (it also gets copied into BOOTRAM due
     // to inclusion in the data copy table below). Note the reference
@@ -552,6 +569,12 @@ data_cpy_table:
 .word __data_start__
 .word __data_end__
 
+#if PICO_RP2040 && PICO_USE_XIP_CACHE_AS_RAM
+.word __xip_ram_text_source__
+.word __xip_ram_text_start__
+.word __xip_ram_text_end__
+#endif
+
 .word __scratch_x_source__
 .word __scratch_x_start__
 .word __scratch_x_end__

src/rp2_common/pico_crt0/rp2040/BUILD.bazel

@@ -4,8 +4,10 @@ exports_files(
     [
         "memmap_blocked_ram.ld",
         "memmap_copy_to_ram.ld",
+        "memmap_copy_to_ram_using_xip_ram.ld",
         "memmap_default.ld",
         "memmap_no_flash.ld",
+        "memmap_no_flash_using_xip_ram.ld",
     ]
 )
 
@@ -45,7 +47,7 @@ cc_library(
 # PICO_BUILD_DEFINE: PICO_COPY_TO_RAM, whether this is a 'copy_to_ram' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link
 cc_library(
     name = "copy_to_ram_linker_script",
-    defines = ["PICO_COPY_TO_RAM=1"],
+    defines = ["PICO_COPY_TO_RAM=1", "PICO_USE_XIP_CACHE_AS_RAM=0"],
     linkopts = ["-T$(location memmap_copy_to_ram.ld)"],
     target_compatible_with = ["//bazel/constraint:rp2040"],
     deps = [
@@ -55,14 +57,39 @@ cc_library(
     ],
 )
 
+# PICO_BUILD_DEFINE: PICO_COPY_TO_RAM && PICO_USE_XIP_CACHE_AS_RAM, whether this is a 'copy_to_ram_using_xip_ram' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link
+cc_library(
+    name = "copy_to_ram_using_xip_ram_linker_script",
+    defines = ["PICO_COPY_TO_RAM=1", "PICO_USE_XIP_CACHE_AS_RAM=1"],
+    linkopts = ["-T$(location memmap_copy_to_ram_using_xip_ram.ld)"],
+    target_compatible_with = ["//bazel/constraint:rp2040"],
+    deps = [
+        "memmap_copy_to_ram_using_xip_ram.ld",
+        "//src/rp2_common/pico_crt0:no_warn_rwx_flag",
+        "//src/rp2_common/pico_standard_link:default_flash_region",
+    ],
+)
+
 # PICO_BUILD_DEFINE: PICO_NO_FLASH, whether this is a 'no_flash' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link
 cc_library(
     name = "no_flash_linker_script",
-    defines = ["PICO_NO_FLASH=1"],
+    defines = ["PICO_NO_FLASH=1", "PICO_USE_XIP_CACHE_AS_RAM=0"],
     linkopts = ["-T$(location memmap_no_flash.ld)"],
     target_compatible_with = ["//bazel/constraint:rp2040"],
     deps = [
         "memmap_no_flash.ld",
         "//src/rp2_common/pico_crt0:no_warn_rwx_flag",
     ],
 )
+
+# PICO_BUILD_DEFINE: PICO_NO_FLASH && PICO_USE_XIP_CACHE_AS_RAM, whether this is a 'no_flash_using_xip_ram' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link
+cc_library(
+    name = "no_flash_using_xip_ram_linker_script",
+    defines = ["PICO_NO_FLASH=1", "PICO_USE_XIP_CACHE_AS_RAM=1"],
+    linkopts = ["-T$(location memmap_no_flash_using_xip_ram.ld)"],
+    target_compatible_with = ["//bazel/constraint:rp2040"],
+    deps = [
+        "memmap_no_flash_using_xip_ram.ld",
+        "//src/rp2_common/pico_crt0:no_warn_rwx_flag",
+    ],
+)

src/rp2_common/pico_crt0/rp2040/memmap_copy_to_ram.ld

@@ -66,7 +66,8 @@ SECTIONS
         KEEP (*(.embedded_block))
         __embedded_block_end = .;
         KEEP (*(.reset))
-    }
+        . = ALIGN(4);
+    } > FLASH
 
     .rodata : {
         /* segments not marked as .flashdata are instead pulled into .data (in RAM) to avoid accidental flash accesses */