GitHub - shgabr/RISC-V-Processor: Implementation of entire RISC-V ISA using Verilog to run on FPGA

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Implementation of entire RISC-V ISA using Verilog to run on FPGA

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
Testing		Testing
report		report
verilog		verilog
readme.txt		readme.txt

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Names: 
	Mina Ashraf Gamil	900182973
	Sherif Hisham Gabr	900183120

Version: V4.0 - MS3&4 Pipelined RISC-V Processor


Assumptions:
	Instructions and Data are separated in memory and should be handled by the user
	

Issues:
	First instruction must be a NOP instruction
	ECALL instruction cannot be placed after a Branch instruction


Need To-Do:
	DONE


Instruction Summary:

  Instructions	  |	  Implemented	  |	      Tested Successful		

	LUI			yes			yes
	AUIPC			yes			yes
	JAL 			yes			yes
	JALR			yes			yes
	BEQ			yes			yes
	BNE			yes			yes
	BLT			yes			yes
	BGE			yes			yes
	BLTU			yes			yes
	BGEU			yes			yes
	LB			yes			yes
	LH			yes			yes
	LW			yes			yes
	LBU			yes			yes
	LHU 			yes			yes
	SB 			yes			yes
	SH 			yes			yes
	SW			yes			yes
	ADDI			yes			yes
	STLI			yes			yes
	SLTIU			yes			yes
	XORI			yes			yes
	ORI			yes			yes
	ANDI			yes			yes
	SLLI			yes			yes
	SRLI			yes			yes
	SRAI			yes			yes
	ADD			yes			yes
	SUB			yes			yes
	SLL			yes			yes
	SLT			yes			yes
	SLTU 			yes			yes
	XOR			yes			yes
	SRL			yes			yes
	SRA			yes			yes
	OR			yes			yes
	AND			yes			yes
	FENCE			yes			yes
	ECALL			yes			yes
	EBREAK			yes			yes





Last Updated: 26 November 2020 - 03:04pm