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@soheilshahrouz soheilshahrouz commented Oct 14, 2025

This PR adds support for inter-die wires defined using the <interdie_wire> tag under <interposer_cut> in the architecture file. The graphics code has been updated accordingly to visualize these wires correctly.

@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool libarchfpga Library for handling FPGA Architecture descriptions docs Documentation lang-cpp C/C++ code labels Oct 14, 2025
@soheilshahrouz soheilshahrouz changed the title [WIP] Add interposer wires Add interposer wires Oct 16, 2025
@AmirhosseinPoolad
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Soheil changed the --device behaviour to be more aligned with the documentation in this PR. While the docs say that if --device is not set, the auto sized device would be selected, previously it would select some fixed size device if there was no auto sized device defined in the architecture file. Now it errors out if --device is not set and there's no auto sized device. This is the reason for the current strong test failure.

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Reviewed until (but not including) draw_rr_edges.cpp so far.

if (!draw_state->show_graphics) {
ezgl::set_disable_event_loop(true);
else
} else {
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Personally I prefe
if () {
// stuff
}
else { // I broke this line.

}

// flag whether the current location is highlighted with a special color or not
bool current_loc_is_highlighted = false;

if (placer_breakpoint_reached()) {
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Could move this into a routine with a proper comment. I think this is checking if we've stopped at a placer breakpoint and if the block is in a special list of blocks to be coloured (due to being part of a move).

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Could move this into a routine with a proper comment. I think this is checking if we've stopped at a placer breakpoint and if the block is in a special list of blocks to be coloured (due to being part of a move).

// since no U-turns from_tracks must be INC as well
x1 = draw_coords->tile_x[to_xlow - 1]
+ draw_coords->get_tile_width();
if (rr_graph.node_direction(from_node) == Direction::DEC) {
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I think commenting why you don't draw from the ends in this case would be good.

vtr::RngContainer& rng,
vtr::NdMatrix<std::vector<t_bottleneck_link>, 2>& interdie_3d_links);

void convert_interposer_cuts_to_sg_patterns(const std::vector<t_layer_def>& interposer_inf,
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Doxygen comment.

static int get_delayless_switch_id(const t_det_routing_arch& det_routing_arch,
bool load_rr_graph);

static void add_and_connect_non_3d_sg_links(RRGraphBuilder& rr_graph_builder,
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Doxygen comment.
Make sure you mention this should only be called once the scatter-gather links/nodes are in the spatial lookup.
And say what the function does.

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Make sure it says you're passing data back through the non_3d_... reference.


vtr::NdMatrix<int, 3>& ptc_matrix = (chan_type == e_rr_type::CHANX) ? chanx_ptc : chany_ptc;

int ptc = 0;
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Explain why you get the max (want to ensure ptc_num is unique along the length of the rr_node we're creating for this sg_link.

const vtr::NdMatrix<std::vector<t_bottleneck_link>, 2>& interdie_3d_links,
int* index);

std::vector<std::pair<RRNodeId, int>> alloc_and_load_non_3d_sg_pattern_rr_node_indices(RRGraphBuilder& rr_graph_builder,
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Doxygen comment.

: CHANX_COST_INDEX_START + num_seg_types_x + link.parallel_segment_index;
rr_graph_builder.set_node_cost_index(node_id, RRIndexedDataId(cons_index));

float R = 0;
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This should come from the segment defined to be used by the sg_link.
Also do the same for CHANZ wires.


VTR_ASSERT_SAFE(src_loc.layer_num == dst_loc.layer_num);
const int layer = src_loc.layer_num;

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could this be refactored with another block of code (which I think was the spatial lookup insertion code) to have a helper once)?


for (size_t i = 0; i < num_links; i++) {

const t_bottleneck_link& link = sg_links[i];
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Comment the overall flow / algorithm of this routine, or the major code blocks.

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Unless the comment at the func declaration has enough detail (once it's written).

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