juncheng edits

2024-09-06.md

@@ -0,0 +1,70 @@
+# gea1000
+
+
+## probability sampling 
+
+### simple random sampling 
+
+randomly assign a person a number and then use a random. number generator to then pick x number 
+
+
+### systematic sampling 
+split the population into groups of k interval e.g populaton is 30 and k = 5 then each group have 6 
+
+then randomly pick one in each group
+
+
+### random stratified sampling 
+
+split population into groups based on characteristics,e.g gender,age group
+
+then randomly pick a member from each group
+
+
+### cluster sampling 
+
+cluster population into clusters based on similarity  and then randomly sample form each cluster 
+
+
+### pros and cons
+
+| Sampling Plan           | Advantages                                          | Disadvantages                                               |
+|-------------------------|----------------------------------------------------|-------------------------------------------------------------|
+| Simple Random Sample     | Good Representation of the Population              | Time-consuming; accessibility of information                |
+| Systematic Sample        | Simpler selection process as opposed to Simple Random Sampling | Potentially under-representing the population                |
+| Stratified Random Sample | Good Representation of Sample by Stratum           | Require Sampling Frame and criteria for classification of population into stratum |
+| Cluster Random Sample    | Less time-consuming and less costly                | Require larger sample size in order to achieve low margin of error |
+
+
+## non probability sampling 
+
+selection is not done using randomness/probability 
+
+
+
+
+
+# data variables 
+
+
+# numerical 
+- discrete 
+- continuous ()
+
+
+# categorical 
+- ordinal  (e.g rating)
+- nominal (e.g name)
+
+
+# experimental groups 
+
+- give a placebo 
+- double blind means subject and asserrs dont know what is what hence no bias 
+
+
+
+
+## identify variables
+
+variabkes used to indenity 

content/Computer Organisation/Combination Circuit/Multiplexer.md

@@ -15,6 +15,31 @@ description:
 ---
 - Short form `Mux`, also known as **data selector**
 - A multiplexer is a [[Combination Circuit]] that selects **one** of **several input signals** and forwards the selected input **into a single line**. It uses **selection lines**(**control signals**) to **choose** which input to send to the output
+- uses $\log_2(2) = 1 bits$ to represent the number of instructions 
+
+### Example of How It mux Works
+
+Let's consider a simple 4-to-1 multiplexer (4 inputs, 1 output):
+
+- **Inputs**: \( I_0, I_1, I_2, I_3 \)
+- **Select Lines**: \( S_1, S_0 \)
+- **Output**: \( Y \)
+
+| \( S_1 \) | \( S_0 \) | Output \( Y \)  |
+|-----------|-----------|-----------------|
+| 0         | 0         | \( I_0 \)       |
+| 0         | 1         | \( I_1 \)       |
+| 1         | 0         | \( I_2 \)       |
+| 1         | 1         | \( I_3 \)       |
+
+In this 4-to-1 MUX:
+- If \( S_1 = 0 \) and \( S_0 = 0 \), the output \( Y \) is \( I_0 \)
+- If \( S_1 = 0 \) and \( S_0 = 1 \), the output \( Y \) is \( I_1 \)
+- If \( S_1 = 1 \) and \( S_0 = 0 \), the output \( Y \) is \( I_2 \)
+- If \( S_1 = 1 \) and \( S_0 = 1 \), the output \( Y \) is \( I_3 \)
+
+---
+
 
 >[!example] General example
 > An **8-to-1 multiplexer** has **8 input lines**, **3 selection lines** (to choose between the 8 inputs), and **1 output line**. Depending on the combination of the selection lines, one of the 8 inputs is connected to the output.

content/Computer Organisation/Instruction Set Architecture (ISA)/MIPS/MIPS I-Type Instruction.md

@@ -11,6 +11,141 @@ References:
 ---
 ## Abstract
 ---
+#### MIPS I-Type Instruction Format
+
+| Field     | Number of Bits | Description                                                                              |
+| --------- | -------------- | ---------------------------------------------------------------------------------------- |
+| opcode    | 6 bits         | Specifies the operation (e.g., load, store, branch)                                      |
+| rs        | 5 bits         | Source register (the register containing the first operand)                              |
+| rt        | 5 bits         | Target register (the register where the result is stored or the immediate value is used) |
+| immediate | 16 bits        | Immediate value or address offset used in the instruction                                |
+
+### Explanation of Each Field
+
+1. **opcode**: 
+   - The first 6 bits indicate the type of operation to be performed.
+
+2. **rs**: 
+   - The next 5 bits specify the source register.
+
+3. **rt**: 
+   - The following 5 bits specify the target register.
+
+4. **immediate**: 
+   - The last 16 bits represent an immediate value or an address offset.
+
+
+### Types of Operations for MIPS I-Type Instructions
+
+1. **Data Transfer Operations**:
+
+    - **Load Word (lw)**: Loads a word from memory into a register.
+    - **Store Word (sw)**: Stores a word from a register into memory.
+    - **Load Byte (lb)**: Loads a byte from memory into a register.
+    - **Store Byte (sb)**: Stores a byte from a register into memory.
+2. **Arithmetic Operations**:
+
+    - **Add Immediate (addi)**: Adds a constant (immediate value) to a register and stores the result in another register.
+    - **Add Immediate Unsigned (addiu)**: Similar to `addi`, but does not check for overflow.
+    - **Subtract Immediate (subi)**: Subtracts an immediate value from a register (not a standard MIPS instruction but can be implemented using `addi` with a negative immediate).
+3. **Logical Operations**:
+
+    - **AND Immediate (andi)**: Performs a bitwise AND operation between a register and an immediate value.
+    - **OR Immediate (ori)**: Performs a bitwise OR operation between a register and an immediate value.
+    - **XOR Immediate (xori)**: Performs a bitwise XOR operation between a register and an immediate value.
+4. **Comparison Operations**:
+
+    - **Set on Less Than Immediate (slti)**: Sets a register to 1 if the value in another register is less than the immediate value; otherwise, it sets the register to 0.
+    - **Set on Less Than Immediate Unsigned (sltiu)**: Similar to `slti`, but treats the values as unsigned.
+5. **Branch Operations**:
+
+    - **Branch on Equal (beq)**: Compares two registers and branches to a specified label if they are equal.
+    - **Branch on Not Equal (bne)**: Compares two registers and branches to a specified label if they are not equal.
+    - **Branch on Less Than (blt)**: Branches to a specified label if the first register is less than the second register.
+    - **Branch on Greater Than (bgt)**: Branches to a specified label if the first register is greater than the second register.
+
+
+
+### MIPS I instruction types 
+
+| Instruction                       | opcode(6 bits) | rs (5 bits) | rt (5 bits) | immediate (16 bits) | Explanation                                                                   |
+| --------------------------------- | -------------- | ----------- | ----------- | ------------------- | ----------------------------------------------------------------------------- |
+| lw (Load Word)                    | 100011         | 00001       | 00010       | 0000000001100100    | Loads a word from memory into register rt.                                    |
+| sw (Store Word)                   | 101011         | 00001       | 00010       | 0000000001100100    | Stores a word from register rt into memory.                                   |
+| addi (Add Immediate)              | 001000         | 00001       | 00010       | 0000000000001010    | Adds an immediate value to register rs and stores in rt.                      |
+| andi (AND Immediate)              | 001100         | 00001       | 00010       | 0000000000001111    | Performs a bitwise AND between register rs and an immediate value.            |
+| ori (OR Immediate)                | 001101         | 00001       | 00010       | 0000000000001111    | Performs a bitwise OR between register rs and an immediate value.             |
+| xori (XOR Immediate)              | 001110         | 00001       | 00010       | 0000000000001111    | Performs a bitwise XOR between register rs and an immediate value.            |
+| slti (Set on Less Than Immediate) | 001010         | 00001       | 00010       | 0000000000001010    | Sets rt to 1 if rs is less than the immediate value; otherwise, sets rt to 0. |
+| beq (Branch on Equal)             | 000100         | 00001       | 00010       | 0000000000000001    | Branches to a label if the values in registers rs and rt are equal.           |
+| bne (Branch on Not Equal)         | 000101         | 00001       | 00010       | 0000000000000001    | Branches to a label if the values in registers rs and rt are not equal.       |
+
+
+## Examples
+---
+### `lw`
+
+- Load Word
+- Loads a word from memory into a register. The address is calculated by adding the immediate value to the value in the source register.
+- The MIPS code: `lw $t2, 100($t1)`
+- The equivalent high-level code: `R[rt] = Memory[R[rs] + SignExtImm]`
+
+### `sw`
+
+- Store Word
+- Stores a word from a register into memory. The address is calculated by adding the immediate value to the value in the source register.
+- The MIPS code: `sw $t2, 100($t1)`
+- The equivalent high-level code: `Memory[R[rs] + SignExtImm] = R[rt]`
+
+### `addi`
+
+- Add Immediate
+- Adds an immediate value to a register and stores the result in another register.
+- The MIPS code: `addi $t2, $t1, 10`
+- The equivalent high-level code: `R[rt] = R[rs] + SignExtImm`
+
+### `andi`
+
+- AND Immediate
+- Performs a bitwise AND operation between a register and an immediate value.
+- The MIPS code: `andi $t2, $t1, 0xFF`
+- The equivalent high-level code: `R[rt] = R[rs] & SignExtImm`
+
+### `ori`
+
+- OR Immediate
+- Performs a bitwise OR operation between a register and an immediate value.
+- The MIPS code: `ori $t2, $t1, 0x0F`
+- The equivalent high-level code: `R[rt] = R[rs] | SignExtImm`
+
+### `xori`
+
+- XOR Immediate
+- Performs a bitwise XOR operation between a register and an immediate value.
+- The MIPS code: `xori $t2, $t1, 0x0F`
+- The equivalent high-level code: `R[rt] = R[rs] ^ SignExtImm`
+
+### `slti`
+
+- Set Less Than Immediate
+- Sets the target register to 1 if the value in the source register is less than the immediate value; otherwise, it sets the target register to 0.
+- The MIPS code: `slti $t2, $t1, 100`
+- The equivalent high-level code: `R[rt] = (R[rs] < SignExtImm) ? 1 : 0`
+
+### `beq`
+
+- Branch on Equal
+- Branches to a specified label if the values in the two registers are equal.
+- The MIPS code: `beq $t1, $t2, label`
+- The equivalent high-level code: `if (R[rs] == R[rt]) PC = PC + SignExtImm`
+
+### `bne`
+
+- Branch on Not Equal
+- Branches to a specified label if the values in the two registers are not equal.
+- The MIPS code: `bne $t1, $t2, label`
+- The equivalent high-level code: `if (R[rs] != R[rt]) PC = PC + SignExtImm`
+=======
 ```
 +--------+-----+-------+-----------------+
 | Opcode |  Rs  |  Rt  |    Immediate    |
@@ -41,6 +176,8 @@ References:
 ### Immediate Value 
 - Value is  [[Integer Encoding (数字编码)#2's Complement (补码)]]
 - 16-bits, can represent up to +-2^15 [[Computer Data Representation#Word]], 2^17 [[Memory Address]] because 4-bytes [[Memory Address#Word Addressing]]
+- to represent longer values can use [[Integer Encoding (数字编码)#sign extension]]
+-  Used for **PC-Relative Addressing**
 - Used for [[ISA Addressing Mode#PC-relative Addressing Mode]]
 
 

content/Computer Organisation/Instruction Set Architecture (ISA)/MIPS/MIPS Instruction.md

@@ -11,6 +11,18 @@ References:
 ---
 ## Abstract
 ---
+
+### mips comes in 3 instruction types 
+![[mips instruct types.jpeg]]
+
+>[!question] why is the source ,target and destination field 5 bits 
+>$2^5 = 32bits$
+>it is because we do operations on the data stored on the register and each register address is 32 bits 
+
+
+
+**32 bits**, the **first 6 bits** are [[Instruction#Opcode]]
+
 - **32 bits**, the **first 6 bits** are [[ISA Instruction Format#Opcode]]
 - There are 3 different format types - [[MIPS R-Type Instruction]], [[MIPS I-Type Instruction]] and [[MIPS J-Type Instruction]]
 
@@ -22,6 +34,14 @@ References:
 
 
 
+
+## Terminologies
+---
+### Op register 
+- 6bits 
+- labeled as op
+- used to specify to the control what operation to perform 
+
 ### Source Register 
 - 5bits
 - Labeled `rs`, mapped to `RR1`
@@ -30,4 +50,7 @@ References:
 - 5 bits
 - Labeled `rt`, mapped to `RR2`
 - [[Register|Register]] with value stored we want to use in [[MIPS R-Type Instruction]]
-- [[Register|Register]] that gets the result of [[Operation]] in [[MIPS I-Type Instruction]]
+- [[Register|Register]] that gets the result of [[Operation]] in [[MIPS I-Type Instruction]]
+
+
+

content/Computer Organisation/Instruction Set Architecture (ISA)/MIPS/MIPS J-Type Instruction.md

@@ -19,9 +19,16 @@ References:
 ```
 
  - [[Instruction]] that tells [[CPU]] jump to [[Memory Address]] & execute [[Instruction]] starting from that point
- - 2 sections - [[ISA Instruction Format#Opcode]] which is always `000010`, [[Memory Address]]
+ - 2 sections - [[Instruction#Opcode]], [[Memory Address]]
  - Supports `if-else` and loops 
- - Label here refers to the **partial target address**
+
+##  MIPS J-Type Instructions
+
+|Instruction|Opcode|Address|Explanation|
+|---|---|---|---|
+|j|000011|26 bits|Jumps to the specified address.|
+|jal|000011|26 bits|Jumps to the specified address and saves the return address in `$ra`.|
+
 
 >[!important] Jump to any address within the same 256 MB region as the current PC
-> Since the MIPS j-type instruction can only store a **26-bit address**, we construct the full 32-bit target address by taking the upper 4 bits from the current [[Register#Program Counter|program counter]], appending the 26-bit immediate from the instruction, and adding **two `0` bits** at the end. We ignore the last 2 bits because MIPS instructions are word-aligned, allowing us to address `256 MB` within the same region of the PC.
+> Since the MIPS j-type instruction can only store a **26-bit address**, we construct the full 32-bit target address by taking the upper 4 bits from the current [[Register#Program Counter|program counter]], appending the 26-bit immediate from the instruction, and adding **two `0` bits** at the end. We ignore the last 2 bits because MIPS instructions are word-aligned, allowing us to address `256 MB` within the same region of the PC.