gatemate: support multiple clock distribution strategies #1574
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gatecat
reviewed
Oct 15, 2025
himbaechel/uarch/gatemate/pack.cc
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| for (auto &user : net->users) { | ||
| IdString die = uarch->index_to_die[uarch->tile_extra_data(net->driver.cell->bel.tile)->die]; | ||
| if (user.cell->region && user.cell->region->name != die) | ||
| log_error("Trying to assing cell '%s' to multiple regions.\n", user.cell->name.c_str(ctx)); |
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| NetInfo *new_signal = ctx->createNet(ctx->idf("%s$die%d", net->name.c_str(ctx), new_die)); | ||
| uarch->glbout[new_die]->connectPort(ctx->id("GLB1"), new_signal); | ||
| copy_constraint(net, new_signal); |
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note to myself as much as anything else - we really need support for clock constraints with phase shifts for timing analysis to work in this kind of situation properly
| iosel->connectPorts(id_GPIO_OUT, gpio, id_A); | ||
| iosel->connectPorts(id_GPIO_EN, gpio, id_T); | ||
| gpio->connectPort(id_IO, new_clk1); | ||
| } else |
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can you add braces to the else clause here too? looks weird without them
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Merged, appreciate it's not so important while multi-die parts are not generally available, but as a follow-up it would be good to document somewhere what these different strategies actually mean. |
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Thanks. Think best place to document that would be in code so will add that. Meanwhile I have pushed clangformat changes since those were missing in xo2 PR. |
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Added a way to specify strategy of clock placement for multi die gatemate.
TODO
Misc: