gatemate: support multiple clock distribution strategies

common/place/placer_heap.cc

@@ -921,8 +921,10 @@ class HeAPPlacer
                     y0 = std::max(y0, r.y0);
                     x1 = std::min(x1, r.x1);
                     y1 = std::min(y1, r.y1);
-                    if (x0 > x1) std::swap(x0, x1);
-                    if (y0 > y1) std::swap(y0, y1);
+                    if (x0 > x1)
+                        std::swap(x0, x1);
+                    if (y0 > y1)
+                        std::swap(y0, y1);
                 }
 
                 // Pick a random X and Y location within our search radius / search box

himbaechel/uarch/gatemate/cells.cc

@@ -125,6 +125,11 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name)
     } else if (type.in(id_CPE_IBUF)) {
         add_port(id_Y, PORT_OUT);
         add_port(id_I, PORT_IN);
+    } else if (type.in(id_CPE_IOBUF)) {
+        add_port(id_Y, PORT_OUT);
+        add_port(id_T, PORT_IN);
+        add_port(id_A, PORT_IN);
+        add_port(id_IO, PORT_INOUT);
     } else if (type.in(id_PLL)) {
         add_port(id_CLK_REF, PORT_IN);
         add_port(id_USR_CLK_REF, PORT_IN);

himbaechel/uarch/gatemate/gatemate.cc

@@ -162,6 +162,7 @@ void GateMateImpl::init(Context *ctx)
     int index = 0;
     for (auto &die : extra->dies) {
         IdString name(die.name);
+        index_to_die[index] = name;
         die_to_index[name] = index++;
         ctx->createRectangularRegion(name, die.x1, die.y1, die.x2, die.y2);
         if (die_name == name.c_str(ctx)) {

himbaechel/uarch/gatemate/gatemate.h

@@ -30,6 +30,13 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+enum MultiDieStrategy
+{
+    CLOCK_MIRROR,
+    REUSE_CLK1,
+    FULL_USE,
+};
+
 struct GateMateImpl : HimbaechelAPI
 {
     ~GateMateImpl();
@@ -91,9 +98,14 @@ struct GateMateImpl : HimbaechelAPI
     int fpga_mode;
     int timing_mode;
     std::map<const NetInfo *, int> global_signals;
+    dict<std::pair<IdString, int>, NetInfo *> global_mapping;
+    dict<std::pair<IdString, int>, IdString> global_clk_mapping;
     std::vector<CellInfo *> clkin;
     std::vector<CellInfo *> glbout;
     std::vector<CellInfo *> pll;
+    pool<IdString> ignore;
+    MultiDieStrategy strategy;
+    dict<int, IdString> index_to_die;
 
   private:
     bool getChildPlacement(const BaseClusterInfo *cluster, Loc root_loc,

himbaechel/uarch/gatemate/pack.cc

@@ -397,15 +397,72 @@ void GateMatePacker::remove_double_constrained()
     }
 }
 
+void GateMatePacker::recursiveAddToRegion(CellInfo *root, IdString die)
+{
+    if (root->region && root->region->name != die)
+        log_error("Trying to assign cell '%s' to multiple regions.\n", root->name.c_str(ctx));
+    ctx->constrainCellToRegion(root->name, die);
+    for (auto cell : root->constr_children) {
+        if (cell->region && cell->region->name != die)
+            log_error("Trying to assign cell '%s' to multiple regions.\n", cell->name.c_str(ctx));
+        ctx->constrainCellToRegion(cell->name, die);
+        recursiveAddToRegion(cell, die);
+    }
+}
+
+void GateMatePacker::assign_clocks()
+{
+    log_info("Assign cells based on clock..\n");
+    for (auto &glob : uarch->global_signals) {
+        const NetInfo *net = glob.first;
+        for (auto &user : net->users) {
+            IdString die = uarch->index_to_die[uarch->tile_extra_data(net->driver.cell->bel.tile)->die];
+            if (user.cell->region && user.cell->region->name != die)
+                log_error("Trying to assign cell '%s' to multiple regions.\n", user.cell->name.c_str(ctx));
+            ctx->constrainCellToRegion(user.cell->name, die);
+            if (user.cell->cluster != ClusterId()) {
+                CellInfo *root = ctx->getClusterRootCell(user.cell->cluster);
+                recursiveAddToRegion(root, die);
+            }
+        }
+    }
+}
+
 void GateMateImpl::pack()
 {
     const ArchArgs &args = ctx->args;
     if (args.options.count("ccf")) {
         parse_ccf(args.options.at("ccf"));
     }
 
-    if (forced_die != IdString())
+    if (args.options.count("multi")) {
+        std::string val = args.options.at("multi");
+        if (val == "mirror") {
+            strategy = MultiDieStrategy::CLOCK_MIRROR;
+            log_info("Multidie mode: CLOCK MIRROR\n");
+        } else if (val == "clk1") {
+            strategy = MultiDieStrategy::REUSE_CLK1;
+            log_info("Multidie mode: REUSE CLK1\n");
+        } else if (val == "full") {
+            strategy = MultiDieStrategy::FULL_USE;
+            log_info("Multidie mode: FULL USE\n");
+        } else {
+            log_error("Unknown value for 'multi' option. Allowed values are 'mirror', 'full' and 'clk1'.\n");
+        }
+    } else {
+        strategy = MultiDieStrategy::CLOCK_MIRROR;
+        if (dies != 1)
+            log_warning("Multi die clock placement strategy set to 'mirror'.\n");
+    }
+
+    if (forced_die != IdString()) {
         preferred_die = die_to_index[forced_die];
+        if (strategy == MultiDieStrategy::FULL_USE)
+            log_error("Not allowed to use forced die in FULL USE mode.\n");
+    }
+
+    if (strategy == MultiDieStrategy::REUSE_CLK1 || strategy == MultiDieStrategy::FULL_USE)
+        preferred_die = 0;
 
     GateMatePacker packer(ctx, this);
     packer.pack_constants();
@@ -431,14 +488,18 @@ void GateMateImpl::pack()
                 ctx->constrainCellToRegion(cell.second->name, forced_die);
         }
     }
+
+    if (strategy == MultiDieStrategy::FULL_USE)
+        packer.assign_clocks();
 }
 
 void GateMateImpl::repack()
 {
     GateMatePacker packer(ctx, this);
     packer.repack_ram();
     packer.repack_cpe();
-    packer.reassign_clocks();
+    if (strategy != MultiDieStrategy::FULL_USE)
+        packer.reassign_clocks();
     packer.remove_clocking();
 }
 

himbaechel/uarch/gatemate/pack.h

@@ -53,7 +53,7 @@ struct GateMatePacker
     void pack_cpe();
     void pack_addf();
     void pack_bufg();
-    void sort_bufg();
+    void sort_bufg(unsigned max_num);
     void insert_clocking();
     void pack_pll();
     void pack_misc();
@@ -71,6 +71,7 @@ struct GateMatePacker
     void repack_ram();
     void reassign_clocks();
     void copy_clocks();
+    void assign_clocks();
 
   private:
     void rename_param(CellInfo *cell, IdString name, IdString new_name, int width);
@@ -88,6 +89,12 @@ struct GateMatePacker
     void move_connections(NetInfo *from_net, NetInfo *to_net);
     void remap_ram_half(CellInfo *half, CellInfo *cell, int num);
 
+    void strategy_mirror();
+    void strategy_clk1();
+    void strategy_full();
+
+    void recursiveAddToRegion(CellInfo *root, IdString die);
+
     PllCfgRecord get_pll_settings(double f_ref, double f_core, int mode, int low_jitter, bool pdiv0_mux, bool feedback);
 
     std::pair<CellInfo *, CellInfo *> move_ram_i(CellInfo *cell, IdString origPort, bool place = true,