cpu/i960: store IRQ line states, immediately return if unchanged #14186
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namcofl.cpp: implement IRQ acks
Machine is responsible for clearing IRQ lines on reset
| const int irq_type[4] = { I960_IRQ0, I960_IRQ1, I960_IRQ2, I960_IRQ3 }; | ||
| for (int i = 0; i < 4; i++) | ||
| { | ||
| m_maincpu->set_input_line(irq_type[i], CLEAR_LINE); | ||
| } |
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Why not move your array of interrupt numbers to an anonymous namespace and make it constexpr so it doesn’t need to be repeated?
Why not use a rang-based for loop here to avoid pitfalls, like
for (auto line : irqs)
m_maincpu->set_input_line(line, CLEAR_LINE);| const int irq_type[4] = { I960_IRQ0, I960_IRQ1, I960_IRQ2, I960_IRQ3 }; | ||
| for (int i = 0; i < 4; i++) | ||
| { | ||
| m_maincpu->set_input_line(irq_type[i], CLEAR_LINE); | ||
| } |
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This is a case for a range-based for loop as well.
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Is it known if the i960 really has this internally rather than having external circuitry doing the job? i.e. is there a page from manual stating so? |
The code as it stands is just a buggy implementation of edge-triggered interrupts. It’s wrong either way. If the chip inherently has edge-triggered interrupts, then this is the correct fix, but it it doesn’t, it should still only be checking for changes, but should clear the condition when it gets the clear line state. As far as I can tell, the 80960 core has level-sensitive interrupts. You need a separate interrupt controller to implement edge-triggered interrupts. However the i960 Jx has an integrated interrupt controller that can be configured for level-sensitive or edge-triggered interrupts. It also has eight interrupt pins, and allows them to be treated as independent interrupt inputs, a bitfield allowing one of 240 interrupt interrupts to be signaled (68k style but with eight pins instead of three), or a hybrid mode with three independent interrupts and five pins used as a bitfield for signaling one of 32 interrupts. What is MAME actually supposed to be emulating here? |
If a particular IRQ line is already high, trying to assert another IRQ on the same line no longer has any effect; the IRQ line must be cleared/lowered first before another IRQ can be asserted.
IRQ acknowledgement logic has been implemented for Namco System FL, since it is now required with the i960 update.