Now tileable rr_graph generator supports subtile pins and z_offset in direct connections

[tangxifan]

Description

The tileable routing resource graph generator provides limited supports on direct connections.
It does not support subtiles and z_offset when direction connections are defined.

Related Issue

Motivation and Context

• Updated the direct connection builder in the tileable rr_graph builder. Now the subtile pins and z_offset are supported.

Here is a quick example on what is now supported.

    <!-- Direct connect from MULT to RAM --> 
    <direct name="direct_mult2ram0_0" from_pin="mult_memory.dataout[9:0]" to_pin="mult_memory.data[9:0]" x_offset="0" y_offset="0" z_offset="1"/>
    <direct name="direct_mult2ram0_1" from_pin="mult_memory.dataout[19:10]" to_pin="mult_memory.data[19:10]" x_offset="0" y_offset="0" z_offset="1"/>
    <direct name="direct_mult2ram0_2" from_pin="mult_memory.dataout[29:20]" to_pin="mult_memory.data[29:20]" x_offset="0" y_offset="0" z_offset="1"/>
    <direct name="direct_mult2ram0_3" from_pin="mult_memory.dataout[39:30]" to_pin="mult_memory.data[39:30]" x_offset="0" y_offset="0" z_offset="1"/>
    <direct name="direct_mult2ram1_0" from_pin="mult_memory.dataout[9:0]" to_pin="mult_memory.data[9:0]" x_offset="0" y_offset="0" z_offset="2"/>
    <direct name="direct_mult2ram1_1" from_pin="mult_memory.dataout[19:10]" to_pin="mult_memory.data[19:10]" x_offset="0" y_offset="0" z_offset="2"/>
    <direct name="direct_mult2ram1_2" from_pin="mult_memory.dataout[29:20]" to_pin="mult_memory.data[29:20]" x_offset="0" y_offset="0" z_offset="2"/>
    <direct name="direct_mult2ram1_3" from_pin="mult_memory.dataout[39:30]" to_pin="mult_memory.data[39:30]" x_offset="0" y_offset="0" z_offset="2"/>

How Has This Been Tested?

• Added a new testcase to the strong regression test, which validates the carry chain connections. This fills the hole where the rudimentary direct connections was not validated in VTR on the tileable rr_graph generator.
• Added a new testcase to the strong regression test, which validates the direct connections between subtiles with a z_offset.

Types of changes

• Bug fix (change which fixes an issue)
• New feature (change which adds functionality)
• Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

• My change requires a change to the documentation
• I have updated the documentation accordingly
• I have added tests to cover my changes
• All new and existing tests passed

[amin1377]

@tangxifan: Is this PR ready for review?

[tangxifan]

@tangxifan: Is this PR ready for review?

Yes. Feel free to comment. We also discuss it in the upcoming weekly meeting.

[tangxifan]

@amin1377 Minor patches applied to resolve CI failures and throw errors when sanity checks failed. It is ready for your review.

[vaughnbetz]

The code looks good to me.
Is there any documentation that needs to be updated to go along with this enhancement (@tangxifan @amin1377 )

[tangxifan]

@vaughnbetz There is no changes required on documentation, as the tileable rr_graph generator supports all the syntax at https://docs.verilogtorouting.org/en/latest/arch/reference/#direct-inter-block-connections

Since tileable rr_graph targets physical modelling of FPGA fabrics, the restrictions (tighter than the regular rr_graph generator) are

• from_pin should appear on only one side of a tile
• to_pin should appear on only one side of a tile
• tileable rr_graph will find the automatically side for both from_pin and to_pin, saving users the effort to specify.

In the code changes of this PR, it will error out with a message if the sanity checks failed.

If you see a must to update the documentation, I will be happy to.

[amin1377]

Thanks, Xifan! It looks good to me.

[vaughnbetz]

Thanks @tangxifan. Sounds good.