Now tileable rr_graph generator supports subtile pins and z_offset in direct connections#3307

amin1377 merged 20 commits intomasterverilog-to-routing/vtr-verilog-to-routing:masterfrom

xt_tileable_direct_fixupverilog-to-routing/vtr-verilog-to-routing:xt_tileable_direct_fixupCopy head branch name to clipboard